From c8b931efb064a7a875df385f469a0ac628fe1d5c Mon Sep 17 00:00:00 2001 From: Andreas Olofsson Date: Wed, 18 Nov 2015 23:26:59 -0500 Subject: [PATCH] Improving the elink_axi environment - Turns out there was a bug hidden in the emaxi that can only be found by properly driving a master device with reads. This could not happen in the old environment. - Note that due to limitations in the esaxi, I had to add the etx_fifo block as an interface (simplest). - The ESAXI is very limited in that it MUST interface to a fifo with spare entries. (so prog_full). This should be FIXED! - Minimal test passes, now to try to reproduce the DMA bug.. --- elink/dv/dut_axi_elink.v | 694 ++++++++++++++++++++++++++++----------- elink/dv/dut_elink.v | 6 +- 2 files changed, 499 insertions(+), 201 deletions(-) diff --git a/elink/dv/dut_axi_elink.v b/elink/dv/dut_axi_elink.v index 27b8d93..3c3e062 100644 --- a/elink/dv/dut_axi_elink.v +++ b/elink/dv/dut_axi_elink.v @@ -79,33 +79,6 @@ module dut(/*AUTOARG*/ /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) wire elink0_chip_nreset; // From elink0 of axi_elink.v - wire [31:0] elink0_m_axi_araddr; // From elink0 of axi_elink.v - wire [1:0] elink0_m_axi_arburst; // From elink0 of axi_elink.v - wire [3:0] elink0_m_axi_arcache; // From elink0 of axi_elink.v - wire [M_IDW-1:0] elink0_m_axi_arid; // From elink0 of axi_elink.v - wire [7:0] elink0_m_axi_arlen; // From elink0 of axi_elink.v - wire elink0_m_axi_arlock; // From elink0 of axi_elink.v - wire [2:0] elink0_m_axi_arprot; // From elink0 of axi_elink.v - wire [3:0] elink0_m_axi_arqos; // From elink0 of axi_elink.v - wire [2:0] elink0_m_axi_arsize; // From elink0 of axi_elink.v - wire elink0_m_axi_arvalid; // From elink0 of axi_elink.v - wire [31:0] elink0_m_axi_awaddr; // From elink0 of axi_elink.v - wire [1:0] elink0_m_axi_awburst; // From elink0 of axi_elink.v - wire [3:0] elink0_m_axi_awcache; // From elink0 of axi_elink.v - wire [M_IDW-1:0] elink0_m_axi_awid; // From elink0 of axi_elink.v - wire [7:0] elink0_m_axi_awlen; // From elink0 of axi_elink.v - wire elink0_m_axi_awlock; // From elink0 of axi_elink.v - wire [2:0] elink0_m_axi_awprot; // From elink0 of axi_elink.v - wire [3:0] elink0_m_axi_awqos; // From elink0 of axi_elink.v - wire [2:0] elink0_m_axi_awsize; // From elink0 of axi_elink.v - wire elink0_m_axi_awvalid; // From elink0 of axi_elink.v - wire elink0_m_axi_bready; // From elink0 of axi_elink.v - wire elink0_m_axi_rready; // From elink0 of axi_elink.v - wire [63:0] elink0_m_axi_wdata; // From elink0 of axi_elink.v - wire [M_IDW-1:0] elink0_m_axi_wid; // From elink0 of axi_elink.v - wire elink0_m_axi_wlast; // From elink0 of axi_elink.v - wire [7:0] elink0_m_axi_wstrb; // From elink0 of axi_elink.v - wire elink0_m_axi_wvalid; // From elink0 of axi_elink.v wire elink0_rxo_rd_wait_n; // From elink0 of axi_elink.v wire elink0_rxo_rd_wait_p; // From elink0 of axi_elink.v wire elink0_rxo_wr_wait_n; // From elink0 of axi_elink.v @@ -124,18 +97,67 @@ module dut(/*AUTOARG*/ wire elink0_txwr_access; // From emesh_if of emesh_if.v wire [PW-1:0] elink0_txwr_packet; // From emesh_if of emesh_if.v wire elink0_txwr_wait; // From emaxi of emaxi.v - wire elink1_chip_nreset; // From elink1 of elink.v - wire elink1_elink_active; // From elink1 of elink.v - wire elink1_rxo_rd_wait_n; // From elink1 of elink.v - wire elink1_rxo_rd_wait_p; // From elink1 of elink.v - wire elink1_rxo_wr_wait_n; // From elink1 of elink.v - wire elink1_rxo_wr_wait_p; // From elink1 of elink.v - wire [7:0] elink1_txo_data_n; // From elink1 of elink.v - wire [7:0] elink1_txo_data_p; // From elink1 of elink.v - wire elink1_txo_frame_n; // From elink1 of elink.v - wire elink1_txo_frame_p; // From elink1 of elink.v - wire elink1_txo_lclk_n; // From elink1 of elink.v - wire elink1_txo_lclk_p; // From elink1 of elink.v + wire elink1_chip_nreset; // From elink1 of axi_elink.v + wire elink1_elink_active; // From elink1 of axi_elink.v + wire [31:0] elink1_m_axi_araddr; // From elink1 of axi_elink.v + wire [1:0] elink1_m_axi_arburst; // From elink1 of axi_elink.v + wire [3:0] elink1_m_axi_arcache; // From elink1 of axi_elink.v + wire [M_IDW-1:0] elink1_m_axi_arid; // From elink1 of axi_elink.v + wire [7:0] elink1_m_axi_arlen; // From elink1 of axi_elink.v + wire elink1_m_axi_arlock; // From elink1 of axi_elink.v + wire [2:0] elink1_m_axi_arprot; // From elink1 of axi_elink.v + wire [3:0] elink1_m_axi_arqos; // From elink1 of axi_elink.v + wire elink1_m_axi_arready; // From esaxi of esaxi.v + wire [2:0] elink1_m_axi_arsize; // From elink1 of axi_elink.v + wire elink1_m_axi_arvalid; // From elink1 of axi_elink.v + wire [31:0] elink1_m_axi_awaddr; // From elink1 of axi_elink.v + wire [1:0] elink1_m_axi_awburst; // From elink1 of axi_elink.v + wire [3:0] elink1_m_axi_awcache; // From elink1 of axi_elink.v + wire [M_IDW-1:0] elink1_m_axi_awid; // From elink1 of axi_elink.v + wire [7:0] elink1_m_axi_awlen; // From elink1 of axi_elink.v + wire elink1_m_axi_awlock; // From elink1 of axi_elink.v + wire [2:0] elink1_m_axi_awprot; // From elink1 of axi_elink.v + wire [3:0] elink1_m_axi_awqos; // From elink1 of axi_elink.v + wire elink1_m_axi_awready; // From esaxi of esaxi.v + wire [2:0] elink1_m_axi_awsize; // From elink1 of axi_elink.v + wire elink1_m_axi_awvalid; // From elink1 of axi_elink.v + wire [S_IDW-1:0] elink1_m_axi_bid; // From esaxi of esaxi.v + wire elink1_m_axi_bready; // From elink1 of axi_elink.v + wire [1:0] elink1_m_axi_bresp; // From esaxi of esaxi.v + wire elink1_m_axi_bvalid; // From esaxi of esaxi.v + wire [31:0] elink1_m_axi_rdata; // From esaxi of esaxi.v + wire [S_IDW-1:0] elink1_m_axi_rid; // From esaxi of esaxi.v + wire elink1_m_axi_rlast; // From esaxi of esaxi.v + wire elink1_m_axi_rready; // From elink1 of axi_elink.v + wire [1:0] elink1_m_axi_rresp; // From esaxi of esaxi.v + wire elink1_m_axi_rvalid; // From esaxi of esaxi.v + wire [63:0] elink1_m_axi_wdata; // From elink1 of axi_elink.v + wire [M_IDW-1:0] elink1_m_axi_wid; // From elink1 of axi_elink.v + wire elink1_m_axi_wlast; // From elink1 of axi_elink.v + wire elink1_m_axi_wready; // From esaxi of esaxi.v + wire [7:0] elink1_m_axi_wstrb; // From elink1 of axi_elink.v + wire elink1_m_axi_wvalid; // From elink1 of axi_elink.v + wire elink1_rxo_rd_wait_n; // From elink1 of axi_elink.v + wire elink1_rxo_rd_wait_p; // From elink1 of axi_elink.v + wire elink1_rxo_wr_wait_n; // From elink1 of axi_elink.v + wire elink1_rxo_wr_wait_p; // From elink1 of axi_elink.v + wire elink1_rxrr_wait; // From esaxi of esaxi.v + wire [7:0] elink1_txo_data_n; // From elink1 of axi_elink.v + wire [7:0] elink1_txo_data_p; // From elink1 of axi_elink.v + wire elink1_txo_frame_n; // From elink1 of axi_elink.v + wire elink1_txo_frame_p; // From elink1 of axi_elink.v + wire elink1_txo_lclk_n; // From elink1 of axi_elink.v + wire elink1_txo_lclk_p; // From elink1 of axi_elink.v + wire elink1_txrd_access; // From esaxi of esaxi.v + wire [PW-1:0] elink1_txrd_packet; // From esaxi of esaxi.v + wire elink1_txwr_access; // From esaxi of esaxi.v + wire [PW-1:0] elink1_txwr_packet; // From esaxi of esaxi.v + wire emem_txrd_access; // From etx_fifo of etx_fifo.v + wire [PW-1:0] emem_txrd_packet; // From etx_fifo of etx_fifo.v + wire emem_txrr_access; // From etx_fifo of etx_fifo.v + wire [PW-1:0] emem_txrr_packet; // From etx_fifo of etx_fifo.v + wire emem_txwr_access; // From etx_fifo of etx_fifo.v + wire [PW-1:0] emem_txwr_packet; // From etx_fifo of etx_fifo.v wire [31:0] m_axi_araddr; // From emaxi of emaxi.v wire [1:0] m_axi_arburst; // From emaxi of emaxi.v wire [3:0] m_axi_arcache; // From emaxi of emaxi.v @@ -174,6 +196,44 @@ module dut(/*AUTOARG*/ wire m_axi_wready; // From elink0 of axi_elink.v wire [7:0] m_axi_wstrb; // From emaxi of emaxi.v wire m_axi_wvalid; // From emaxi of emaxi.v + wire [31:0] stub_m_axi_araddr; // From elink0 of axi_elink.v, ... + wire [1:0] stub_m_axi_arburst; // From elink0 of axi_elink.v, ... + wire [3:0] stub_m_axi_arcache; // From elink0 of axi_elink.v, ... + wire [M_IDW-1:0] stub_m_axi_arid; // From elink0 of axi_elink.v, ... + wire [7:0] stub_m_axi_arlen; // From elink0 of axi_elink.v, ... + wire stub_m_axi_arlock; // From elink0 of axi_elink.v, ... + wire [2:0] stub_m_axi_arprot; // From elink0 of axi_elink.v, ... + wire [3:0] stub_m_axi_arqos; // From elink0 of axi_elink.v, ... + wire stub_m_axi_arready; // From axislave_stub of axislave_stub.v, ... + wire [2:0] stub_m_axi_arsize; // From elink0 of axi_elink.v, ... + wire stub_m_axi_arvalid; // From elink0 of axi_elink.v, ... + wire [31:0] stub_m_axi_awaddr; // From elink0 of axi_elink.v, ... + wire [1:0] stub_m_axi_awburst; // From elink0 of axi_elink.v, ... + wire [3:0] stub_m_axi_awcache; // From elink0 of axi_elink.v, ... + wire [M_IDW-1:0] stub_m_axi_awid; // From elink0 of axi_elink.v, ... + wire [7:0] stub_m_axi_awlen; // From elink0 of axi_elink.v, ... + wire stub_m_axi_awlock; // From elink0 of axi_elink.v, ... + wire [2:0] stub_m_axi_awprot; // From elink0 of axi_elink.v, ... + wire [3:0] stub_m_axi_awqos; // From elink0 of axi_elink.v, ... + wire stub_m_axi_awready; // From axislave_stub of axislave_stub.v, ... + wire [2:0] stub_m_axi_awsize; // From elink0 of axi_elink.v, ... + wire stub_m_axi_awvalid; // From elink0 of axi_elink.v, ... + wire [S_IDW-1:0] stub_m_axi_bid; // From axislave_stub of axislave_stub.v, ... + wire stub_m_axi_bready; // From elink0 of axi_elink.v, ... + wire [1:0] stub_m_axi_bresp; // From axislave_stub of axislave_stub.v, ... + wire stub_m_axi_bvalid; // From axislave_stub of axislave_stub.v, ... + wire [31:0] stub_m_axi_rdata; // From axislave_stub of axislave_stub.v, ... + wire [S_IDW-1:0] stub_m_axi_rid; // From axislave_stub of axislave_stub.v, ... + wire stub_m_axi_rlast; // From axislave_stub of axislave_stub.v, ... + wire stub_m_axi_rready; // From elink0 of axi_elink.v, ... + wire [1:0] stub_m_axi_rresp; // From axislave_stub of axislave_stub.v, ... + wire stub_m_axi_rvalid; // From axislave_stub of axislave_stub.v, ... + wire [63:0] stub_m_axi_wdata; // From elink0 of axi_elink.v, ... + wire [M_IDW-1:0] stub_m_axi_wid; // From elink0 of axi_elink.v, ... + wire stub_m_axi_wlast; // From elink0 of axi_elink.v, ... + wire stub_m_axi_wready; // From axislave_stub of axislave_stub.v, ... + wire [7:0] stub_m_axi_wstrb; // From elink0 of axi_elink.v, ... + wire stub_m_axi_wvalid; // From elink0 of axi_elink.v, ... // End of automatics @@ -197,7 +257,6 @@ module dut(/*AUTOARG*/ ); */ - emesh_if #(.PW(PW)) emesh_if (.c2e_rmesh_access_in(1'b0), .c2e_rmesh_packet_in({(PW){1'b0}}), @@ -229,7 +288,7 @@ module dut(/*AUTOARG*/ //###################################################################### - //AXI MASTER + //AXI MASTER (DRIVES STIMULUS) //###################################################################### /*emaxi AUTO_TEMPLATE (//Stimulus .rxwr_access (elink0_txwr_access), @@ -246,7 +305,7 @@ module dut(/*AUTOARG*/ */ - + emaxi #(.M_IDW(M_IDW)) emaxi (.m_axi_aclk (clk), .m_axi_aresetn (nreset), @@ -301,8 +360,7 @@ module dut(/*AUTOARG*/ .m_axi_rlast (m_axi_rlast), .m_axi_rvalid (m_axi_rvalid)); - - + //###################################################################### //1ST ELINK //###################################################################### @@ -315,28 +373,23 @@ module dut(/*AUTOARG*/ .rxi_\(.*\) (elink1_txo_\1[]), .txi_\(.*\) (elink1_rxo_\1[]), .s_\(.*\) (m_\1[]), + .m_\(.*\) (stub_m_\1[]), .\(.*\) (@"(substring vl-cell-name 0 6)"_\1[]), ); */ + defparam elink0.ID = 12'h810; - defparam elink0.ETYPE = 0; - axi_elink elink0 (.s_axi_aresetn (nreset), - .sys_nreset (nreset), + defparam elink0.ETYPE = 0; + defparam elink0.M_IDW = M_IDW; + defparam elink0.S_IDW = S_IDW; + + axi_elink elink0 (//!!!!!!!!!!64b-->32bi interface HACK + .s_axi_wstrb ( m_axi_wstrb[3:0] | m_axi_wstrb[7:4] ), + .s_axi_aresetn (nreset), + .sys_nreset (nreset), + .m_axi_aresetn (nreset), .elink_active (dut_active), - .s_axi_wstrb (m_axi_wstrb[3:0] | m_axi_wstrb[7:4]),//64b-->32bi interface HACK - .m_axi_aresetn (1'b1), - .m_axi_awready (1'b0), - .m_axi_wready (1'b0), - .m_axi_bvalid (1'b0), - .m_axi_arready (1'b0), - .m_axi_rlast (1'b0), - .m_axi_rvalid (1'b0), - .m_axi_bid (6'b0), - .m_axi_bresp (2'b0), - .m_axi_rid (6'b0), - .m_axi_rdata (64'b0), - .m_axi_rresp (2'b0), /*AUTOINST*/ // Outputs .rxo_wr_wait_p (elink0_rxo_wr_wait_p), // Templated @@ -355,33 +408,33 @@ module dut(/*AUTOARG*/ .cclk_n (elink0_cclk_n), // Templated .mailbox_not_empty (elink0_mailbox_not_empty), // Templated .mailbox_full (elink0_mailbox_full), // Templated - .m_axi_awid (elink0_m_axi_awid[M_IDW-1:0]), // Templated - .m_axi_awaddr (elink0_m_axi_awaddr[31:0]), // Templated - .m_axi_awlen (elink0_m_axi_awlen[7:0]), // Templated - .m_axi_awsize (elink0_m_axi_awsize[2:0]), // Templated - .m_axi_awburst (elink0_m_axi_awburst[1:0]), // Templated - .m_axi_awlock (elink0_m_axi_awlock), // Templated - .m_axi_awcache (elink0_m_axi_awcache[3:0]), // Templated - .m_axi_awprot (elink0_m_axi_awprot[2:0]), // Templated - .m_axi_awqos (elink0_m_axi_awqos[3:0]), // Templated - .m_axi_awvalid (elink0_m_axi_awvalid), // Templated - .m_axi_wid (elink0_m_axi_wid[M_IDW-1:0]), // Templated - .m_axi_wdata (elink0_m_axi_wdata[63:0]), // Templated - .m_axi_wstrb (elink0_m_axi_wstrb[7:0]), // Templated - .m_axi_wlast (elink0_m_axi_wlast), // Templated - .m_axi_wvalid (elink0_m_axi_wvalid), // Templated - .m_axi_bready (elink0_m_axi_bready), // Templated - .m_axi_arid (elink0_m_axi_arid[M_IDW-1:0]), // Templated - .m_axi_araddr (elink0_m_axi_araddr[31:0]), // Templated - .m_axi_arlen (elink0_m_axi_arlen[7:0]), // Templated - .m_axi_arsize (elink0_m_axi_arsize[2:0]), // Templated - .m_axi_arburst (elink0_m_axi_arburst[1:0]), // Templated - .m_axi_arlock (elink0_m_axi_arlock), // Templated - .m_axi_arcache (elink0_m_axi_arcache[3:0]), // Templated - .m_axi_arprot (elink0_m_axi_arprot[2:0]), // Templated - .m_axi_arqos (elink0_m_axi_arqos[3:0]), // Templated - .m_axi_arvalid (elink0_m_axi_arvalid), // Templated - .m_axi_rready (elink0_m_axi_rready), // Templated + .m_axi_awid (stub_m_axi_awid[M_IDW-1:0]), // Templated + .m_axi_awaddr (stub_m_axi_awaddr[31:0]), // Templated + .m_axi_awlen (stub_m_axi_awlen[7:0]), // Templated + .m_axi_awsize (stub_m_axi_awsize[2:0]), // Templated + .m_axi_awburst (stub_m_axi_awburst[1:0]), // Templated + .m_axi_awlock (stub_m_axi_awlock), // Templated + .m_axi_awcache (stub_m_axi_awcache[3:0]), // Templated + .m_axi_awprot (stub_m_axi_awprot[2:0]), // Templated + .m_axi_awqos (stub_m_axi_awqos[3:0]), // Templated + .m_axi_awvalid (stub_m_axi_awvalid), // Templated + .m_axi_wid (stub_m_axi_wid[M_IDW-1:0]), // Templated + .m_axi_wdata (stub_m_axi_wdata[63:0]), // Templated + .m_axi_wstrb (stub_m_axi_wstrb[7:0]), // Templated + .m_axi_wlast (stub_m_axi_wlast), // Templated + .m_axi_wvalid (stub_m_axi_wvalid), // Templated + .m_axi_bready (stub_m_axi_bready), // Templated + .m_axi_arid (stub_m_axi_arid[M_IDW-1:0]), // Templated + .m_axi_araddr (stub_m_axi_araddr[31:0]), // Templated + .m_axi_arlen (stub_m_axi_arlen[7:0]), // Templated + .m_axi_arsize (stub_m_axi_arsize[2:0]), // Templated + .m_axi_arburst (stub_m_axi_arburst[1:0]), // Templated + .m_axi_arlock (stub_m_axi_arlock), // Templated + .m_axi_arcache (stub_m_axi_arcache[3:0]), // Templated + .m_axi_arprot (stub_m_axi_arprot[2:0]), // Templated + .m_axi_arqos (stub_m_axi_arqos[3:0]), // Templated + .m_axi_arvalid (stub_m_axi_arvalid), // Templated + .m_axi_rready (stub_m_axi_rready), // Templated .s_axi_arready (m_axi_arready), // Templated .s_axi_awready (m_axi_awready), // Templated .s_axi_bid (m_axi_bid[S_IDW-1:0]), // Templated @@ -406,6 +459,17 @@ module dut(/*AUTOARG*/ .txi_wr_wait_n (elink1_rxo_wr_wait_n), // Templated .txi_rd_wait_p (elink1_rxo_rd_wait_p), // Templated .txi_rd_wait_n (elink1_rxo_rd_wait_n), // Templated + .m_axi_awready (stub_m_axi_awready), // Templated + .m_axi_wready (stub_m_axi_wready), // Templated + .m_axi_bid (stub_m_axi_bid[M_IDW-1:0]), // Templated + .m_axi_bresp (stub_m_axi_bresp[1:0]), // Templated + .m_axi_bvalid (stub_m_axi_bvalid), // Templated + .m_axi_arready (stub_m_axi_arready), // Templated + .m_axi_rid (stub_m_axi_rid[M_IDW-1:0]), // Templated + .m_axi_rdata (stub_m_axi_rdata[63:0]), // Templated + .m_axi_rresp (stub_m_axi_rresp[1:0]), // Templated + .m_axi_rlast (stub_m_axi_rlast), // Templated + .m_axi_rvalid (stub_m_axi_rvalid), // Templated .s_axi_arid (m_axi_arid[S_IDW-1:0]), // Templated .s_axi_araddr (m_axi_araddr[31:0]), // Templated .s_axi_arburst (m_axi_arburst[1:0]), // Templated @@ -433,148 +497,384 @@ module dut(/*AUTOARG*/ .s_axi_wlast (m_axi_wlast), // Templated .s_axi_wvalid (m_axi_wvalid)); // Templated + //###################################################################### + //TIE OFF UNUSED MASTER PORT ON ELINK0 + //###################################################################### + /*axislave_stub AUTO_TEMPLATE ( + // Outputs + .s_\(.*\) (stub_m_\1[]), + ); + */ + defparam axislave_stub.S_IDW = S_IDW; - //###################################################################### - //2ND ELINK (WITH EPIPHANY MEMORY) - //###################################################################### - //Fifo hack to avoid waits... - wire [PW-1:0] elink1_txwr_packet; + axislave_stub axislave_stub (.s_axi_aclk (clk), + .s_axi_aresetn (nreset), + /*AUTOINST*/ + // Outputs + .s_axi_arready (stub_m_axi_arready), // Templated + .s_axi_awready (stub_m_axi_awready), // Templated + .s_axi_bid (stub_m_axi_bid[S_IDW-1:0]), // Templated + .s_axi_bresp (stub_m_axi_bresp[1:0]), // Templated + .s_axi_bvalid (stub_m_axi_bvalid), // Templated + .s_axi_rid (stub_m_axi_rid[S_IDW-1:0]), // Templated + .s_axi_rdata (stub_m_axi_rdata[31:0]), // Templated + .s_axi_rlast (stub_m_axi_rlast), // Templated + .s_axi_rresp (stub_m_axi_rresp[1:0]), // Templated + .s_axi_rvalid (stub_m_axi_rvalid), // Templated + .s_axi_wready (stub_m_axi_wready), // Templated + // Inputs + .s_axi_arid (stub_m_axi_arid[S_IDW-1:0]), // Templated + .s_axi_araddr (stub_m_axi_araddr[31:0]), // Templated + .s_axi_arburst (stub_m_axi_arburst[1:0]), // Templated + .s_axi_arcache (stub_m_axi_arcache[3:0]), // Templated + .s_axi_arlock (stub_m_axi_arlock), // Templated + .s_axi_arlen (stub_m_axi_arlen[7:0]), // Templated + .s_axi_arprot (stub_m_axi_arprot[2:0]), // Templated + .s_axi_arqos (stub_m_axi_arqos[3:0]), // Templated + .s_axi_arsize (stub_m_axi_arsize[2:0]), // Templated + .s_axi_arvalid (stub_m_axi_arvalid), // Templated + .s_axi_awid (stub_m_axi_awid[S_IDW-1:0]), // Templated + .s_axi_awaddr (stub_m_axi_awaddr[31:0]), // Templated + .s_axi_awburst (stub_m_axi_awburst[1:0]), // Templated + .s_axi_awcache (stub_m_axi_awcache[3:0]), // Templated + .s_axi_awlock (stub_m_axi_awlock), // Templated + .s_axi_awlen (stub_m_axi_awlen[7:0]), // Templated + .s_axi_awprot (stub_m_axi_awprot[2:0]), // Templated + .s_axi_awqos (stub_m_axi_awqos[3:0]), // Templated + .s_axi_awsize (stub_m_axi_awsize[2:0]), // Templated + .s_axi_awvalid (stub_m_axi_awvalid), // Templated + .s_axi_bready (stub_m_axi_bready), // Templated + .s_axi_rready (stub_m_axi_rready), // Templated + .s_axi_wid (stub_m_axi_wid[S_IDW-1:0]), // Templated + .s_axi_wdata (stub_m_axi_wdata[31:0]), // Templated + .s_axi_wlast (stub_m_axi_wlast), // Templated + .s_axi_wstrb (stub_m_axi_wstrb[3:0]), // Templated + .s_axi_wvalid (stub_m_axi_wvalid)); // Templated - fifo_cdc - #(.DW(104), - .DEPTH(32)) - fifo_cdc ( - // Outputs - .wait_out (), - .access_out (elink1_txwr_access), - .packet_out (elink1_txwr_packet[PW-1:0]), - // Inputs - .nreset (nreset), - .clk_in (clk), - .access_in (elink0_txwr_access & (elink0_txwr_packet[39:24]==16'h820f)), - .packet_in (elink0_txwr_packet[PW-1:0]), - .clk_out (clk), - .wait_in (elink1_txwr_wait)); - - /*elink AUTO_TEMPLATE ( + //###################################################################### + //2ND ELINK + //###################################################################### + + /*axi_elink AUTO_TEMPLATE ( // Outputs .sys_clk (clk), - .sys_nreset (nreset), - .rxi_\(.*\) (elink0_txo_\1[]), - .txi_\(.*\) (elink0_rxo_\1[]), + .rxi_\(.*\) (elink1_txo_\1[]), + .txi_\(.*\) (elink1_rxo_\1[]), + .s_\(.*\) (stub_m_\1[]), + .m_\(.*\) (elink1_m_\1[]), .\(.*\) (@"(substring vl-cell-name 0 6)"_\1[]), - ) - */ - //No read/write from elink1 (for now) - assign elink1_txrd_access = 1'b0; - assign elink1_txrd_packet = 'b0; - assign elink1_rxrr_wait = 1'b0; - - defparam elink1.ID = 12'h820; + ); + */ + + defparam elink1.ID = 12'h820; defparam elink1.ETYPE = 0; + defparam elink1.S_IDW = S_IDW; + defparam elink1.M_IDW = M_IDW; + + axi_elink elink1 ( .m_axi_rdata ({elink1_m_axi_rdata[31:0],elink1_m_axi_rdata[31:0]}), + .m_axi_aresetn (nreset), + .s_axi_aresetn (nreset), + .sys_nreset (nreset), + .rxi_lclk_p (elink0_txo_lclk_p), + .rxi_lclk_n (elink0_txo_lclk_n), + .rxi_frame_p (elink0_txo_frame_p), + .rxi_frame_n (elink0_txo_frame_n), + .rxi_data_p (elink0_txo_data_p[7:0]), + .rxi_data_n (elink0_txo_data_n[7:0]), + .txi_wr_wait_p (elink0_rxo_wr_wait_p), + .txi_wr_wait_n (elink0_rxo_wr_wait_n), + .txi_rd_wait_p (elink0_rxo_rd_wait_p), + .txi_rd_wait_n (elink0_rxo_rd_wait_n), + /*AUTOINST*/ + // Outputs + .elink_active (elink1_elink_active), // Templated + .rxo_wr_wait_p (elink1_rxo_wr_wait_p), // Templated + .rxo_wr_wait_n (elink1_rxo_wr_wait_n), // Templated + .rxo_rd_wait_p (elink1_rxo_rd_wait_p), // Templated + .rxo_rd_wait_n (elink1_rxo_rd_wait_n), // Templated + .txo_lclk_p (elink1_txo_lclk_p), // Templated + .txo_lclk_n (elink1_txo_lclk_n), // Templated + .txo_frame_p (elink1_txo_frame_p), // Templated + .txo_frame_n (elink1_txo_frame_n), // Templated + .txo_data_p (elink1_txo_data_p[7:0]), // Templated + .txo_data_n (elink1_txo_data_n[7:0]), // Templated + .chipid (elink1_chipid[11:0]), // Templated + .chip_nreset (elink1_chip_nreset), // Templated + .cclk_p (elink1_cclk_p), // Templated + .cclk_n (elink1_cclk_n), // Templated + .mailbox_not_empty (elink1_mailbox_not_empty), // Templated + .mailbox_full (elink1_mailbox_full), // Templated + .m_axi_awid (elink1_m_axi_awid[M_IDW-1:0]), // Templated + .m_axi_awaddr (elink1_m_axi_awaddr[31:0]), // Templated + .m_axi_awlen (elink1_m_axi_awlen[7:0]), // Templated + .m_axi_awsize (elink1_m_axi_awsize[2:0]), // Templated + .m_axi_awburst (elink1_m_axi_awburst[1:0]), // Templated + .m_axi_awlock (elink1_m_axi_awlock), // Templated + .m_axi_awcache (elink1_m_axi_awcache[3:0]), // Templated + .m_axi_awprot (elink1_m_axi_awprot[2:0]), // Templated + .m_axi_awqos (elink1_m_axi_awqos[3:0]), // Templated + .m_axi_awvalid (elink1_m_axi_awvalid), // Templated + .m_axi_wid (elink1_m_axi_wid[M_IDW-1:0]), // Templated + .m_axi_wdata (elink1_m_axi_wdata[63:0]), // Templated + .m_axi_wstrb (elink1_m_axi_wstrb[7:0]), // Templated + .m_axi_wlast (elink1_m_axi_wlast), // Templated + .m_axi_wvalid (elink1_m_axi_wvalid), // Templated + .m_axi_bready (elink1_m_axi_bready), // Templated + .m_axi_arid (elink1_m_axi_arid[M_IDW-1:0]), // Templated + .m_axi_araddr (elink1_m_axi_araddr[31:0]), // Templated + .m_axi_arlen (elink1_m_axi_arlen[7:0]), // Templated + .m_axi_arsize (elink1_m_axi_arsize[2:0]), // Templated + .m_axi_arburst (elink1_m_axi_arburst[1:0]), // Templated + .m_axi_arlock (elink1_m_axi_arlock), // Templated + .m_axi_arcache (elink1_m_axi_arcache[3:0]), // Templated + .m_axi_arprot (elink1_m_axi_arprot[2:0]), // Templated + .m_axi_arqos (elink1_m_axi_arqos[3:0]), // Templated + .m_axi_arvalid (elink1_m_axi_arvalid), // Templated + .m_axi_rready (elink1_m_axi_rready), // Templated + .s_axi_arready (stub_m_axi_arready), // Templated + .s_axi_awready (stub_m_axi_awready), // Templated + .s_axi_bid (stub_m_axi_bid[S_IDW-1:0]), // Templated + .s_axi_bresp (stub_m_axi_bresp[1:0]), // Templated + .s_axi_bvalid (stub_m_axi_bvalid), // Templated + .s_axi_rid (stub_m_axi_rid[S_IDW-1:0]), // Templated + .s_axi_rdata (stub_m_axi_rdata[31:0]), // Templated + .s_axi_rlast (stub_m_axi_rlast), // Templated + .s_axi_rresp (stub_m_axi_rresp[1:0]), // Templated + .s_axi_rvalid (stub_m_axi_rvalid), // Templated + .s_axi_wready (stub_m_axi_wready), // Templated + .timeout (elink1_timeout), // Templated + // Inputs + .sys_clk (clk), // Templated + .m_axi_awready (elink1_m_axi_awready), // Templated + .m_axi_wready (elink1_m_axi_wready), // Templated + .m_axi_bid (elink1_m_axi_bid[M_IDW-1:0]), // Templated + .m_axi_bresp (elink1_m_axi_bresp[1:0]), // Templated + .m_axi_bvalid (elink1_m_axi_bvalid), // Templated + .m_axi_arready (elink1_m_axi_arready), // Templated + .m_axi_rid (elink1_m_axi_rid[M_IDW-1:0]), // Templated + .m_axi_rresp (elink1_m_axi_rresp[1:0]), // Templated + .m_axi_rlast (elink1_m_axi_rlast), // Templated + .m_axi_rvalid (elink1_m_axi_rvalid), // Templated + .s_axi_arid (stub_m_axi_arid[S_IDW-1:0]), // Templated + .s_axi_araddr (stub_m_axi_araddr[31:0]), // Templated + .s_axi_arburst (stub_m_axi_arburst[1:0]), // Templated + .s_axi_arcache (stub_m_axi_arcache[3:0]), // Templated + .s_axi_arlock (stub_m_axi_arlock), // Templated + .s_axi_arlen (stub_m_axi_arlen[7:0]), // Templated + .s_axi_arprot (stub_m_axi_arprot[2:0]), // Templated + .s_axi_arqos (stub_m_axi_arqos[3:0]), // Templated + .s_axi_arsize (stub_m_axi_arsize[2:0]), // Templated + .s_axi_arvalid (stub_m_axi_arvalid), // Templated + .s_axi_awid (stub_m_axi_awid[S_IDW-1:0]), // Templated + .s_axi_awaddr (stub_m_axi_awaddr[31:0]), // Templated + .s_axi_awburst (stub_m_axi_awburst[1:0]), // Templated + .s_axi_awcache (stub_m_axi_awcache[3:0]), // Templated + .s_axi_awlock (stub_m_axi_awlock), // Templated + .s_axi_awlen (stub_m_axi_awlen[7:0]), // Templated + .s_axi_awprot (stub_m_axi_awprot[2:0]), // Templated + .s_axi_awqos (stub_m_axi_awqos[3:0]), // Templated + .s_axi_awsize (stub_m_axi_awsize[2:0]), // Templated + .s_axi_awvalid (stub_m_axi_awvalid), // Templated + .s_axi_bready (stub_m_axi_bready), // Templated + .s_axi_rready (stub_m_axi_rready), // Templated + .s_axi_wid (stub_m_axi_wid[S_IDW-1:0]), // Templated + .s_axi_wdata (stub_m_axi_wdata[31:0]), // Templated + .s_axi_wlast (stub_m_axi_wlast), // Templated + .s_axi_wstrb (stub_m_axi_wstrb[3:0]), // Templated + .s_axi_wvalid (stub_m_axi_wvalid)); // Templated - elink elink1 (//Hack for configuring 2nd link - .txwr_access (elink1_txwr_access), - .txwr_packet (elink1_txwr_packet[PW-1:0]), - .txrd_access (1'b0), - .txrd_packet ({(PW){1'b0}}), - .txrr_access (elink1_txrr_access), - .txrr_packet (elink1_txrr_packet[PW-1:0]), - .rxrr_wait (1'b0), - /*AUTOINST*/ - // Outputs - .elink_active (elink1_elink_active), // Templated - .rxo_wr_wait_p (elink1_rxo_wr_wait_p), // Templated - .rxo_wr_wait_n (elink1_rxo_wr_wait_n), // Templated - .rxo_rd_wait_p (elink1_rxo_rd_wait_p), // Templated - .rxo_rd_wait_n (elink1_rxo_rd_wait_n), // Templated - .txo_lclk_p (elink1_txo_lclk_p), // Templated - .txo_lclk_n (elink1_txo_lclk_n), // Templated - .txo_frame_p (elink1_txo_frame_p), // Templated - .txo_frame_n (elink1_txo_frame_n), // Templated - .txo_data_p (elink1_txo_data_p[7:0]), // Templated - .txo_data_n (elink1_txo_data_n[7:0]), // Templated - .chipid (elink1_chipid[11:0]), // Templated - .cclk_p (elink1_cclk_p), // Templated - .cclk_n (elink1_cclk_n), // Templated - .chip_nreset (elink1_chip_nreset), // Templated - .mailbox_not_empty (elink1_mailbox_not_empty), // Templated - .mailbox_full (elink1_mailbox_full), // Templated - .timeout (elink1_timeout), // Templated - .rxwr_access (elink1_rxwr_access), // Templated - .rxwr_packet (elink1_rxwr_packet[PW-1:0]), // Templated - .rxrd_access (elink1_rxrd_access), // Templated - .rxrd_packet (elink1_rxrd_packet[PW-1:0]), // Templated - .rxrr_access (elink1_rxrr_access), // Templated - .rxrr_packet (elink1_rxrr_packet[PW-1:0]), // Templated - .txwr_wait (elink1_txwr_wait), // Templated - .txrd_wait (elink1_txrd_wait), // Templated - .txrr_wait (elink1_txrr_wait), // Templated - // Inputs - .sys_nreset (nreset), // Templated - .sys_clk (clk), // Templated - .rxi_lclk_p (elink0_txo_lclk_p), // Templated - .rxi_lclk_n (elink0_txo_lclk_n), // Templated - .rxi_frame_p (elink0_txo_frame_p), // Templated - .rxi_frame_n (elink0_txo_frame_n), // Templated - .rxi_data_p (elink0_txo_data_p[7:0]), // Templated - .rxi_data_n (elink0_txo_data_n[7:0]), // Templated - .txi_wr_wait_p (elink0_rxo_wr_wait_p), // Templated - .txi_wr_wait_n (elink0_rxo_wr_wait_n), // Templated - .txi_rd_wait_p (elink0_rxo_rd_wait_p), // Templated - .txi_rd_wait_n (elink0_rxo_rd_wait_n), // Templated - .rxwr_wait (elink1_rxwr_wait), // Templated - .rxrd_wait (elink1_rxrd_wait)); // Templated + //###################################################################### + //TIE OFF UNUSED SLAVE PORT ON ELINK1 + //###################################################################### + + /*aximaster_stub AUTO_TEMPLATE ( + // Outputs + .m_\(.*\) (stub_m_\1[]), + ); + */ + aximaster_stub + #(.M_IDW(M_IDW)) + aximaster_stub (.m_axi_aclk (aclk), + .m_axi_aresetn (nreset), + /*AUTOINST*/ + // Outputs + .m_axi_awid (stub_m_axi_awid[M_IDW-1:0]), // Templated + .m_axi_awaddr (stub_m_axi_awaddr[31:0]), // Templated + .m_axi_awlen (stub_m_axi_awlen[7:0]), // Templated + .m_axi_awsize (stub_m_axi_awsize[2:0]), // Templated + .m_axi_awburst (stub_m_axi_awburst[1:0]), // Templated + .m_axi_awlock (stub_m_axi_awlock), // Templated + .m_axi_awcache (stub_m_axi_awcache[3:0]), // Templated + .m_axi_awprot (stub_m_axi_awprot[2:0]), // Templated + .m_axi_awqos (stub_m_axi_awqos[3:0]), // Templated + .m_axi_awvalid (stub_m_axi_awvalid), // Templated + .m_axi_wid (stub_m_axi_wid[M_IDW-1:0]), // Templated + .m_axi_wdata (stub_m_axi_wdata[63:0]), // Templated + .m_axi_wstrb (stub_m_axi_wstrb[7:0]), // Templated + .m_axi_wlast (stub_m_axi_wlast), // Templated + .m_axi_wvalid (stub_m_axi_wvalid), // Templated + .m_axi_bready (stub_m_axi_bready), // Templated + .m_axi_arid (stub_m_axi_arid[M_IDW-1:0]), // Templated + .m_axi_araddr (stub_m_axi_araddr[31:0]), // Templated + .m_axi_arlen (stub_m_axi_arlen[7:0]), // Templated + .m_axi_arsize (stub_m_axi_arsize[2:0]), // Templated + .m_axi_arburst (stub_m_axi_arburst[1:0]), // Templated + .m_axi_arlock (stub_m_axi_arlock), // Templated + .m_axi_arcache (stub_m_axi_arcache[3:0]), // Templated + .m_axi_arprot (stub_m_axi_arprot[2:0]), // Templated + .m_axi_arqos (stub_m_axi_arqos[3:0]), // Templated + .m_axi_arvalid (stub_m_axi_arvalid), // Templated + .m_axi_rready (stub_m_axi_rready), // Templated + // Inputs + .m_axi_awready (stub_m_axi_awready), // Templated + .m_axi_wready (stub_m_axi_wready), // Templated + .m_axi_bid (stub_m_axi_bid[M_IDW-1:0]), // Templated + .m_axi_bresp (stub_m_axi_bresp[1:0]), // Templated + .m_axi_bvalid (stub_m_axi_bvalid), // Templated + .m_axi_arready (stub_m_axi_arready), // Templated + .m_axi_rid (stub_m_axi_rid[M_IDW-1:0]), // Templated + .m_axi_rdata (stub_m_axi_rdata[63:0]), // Templated + .m_axi_rresp (stub_m_axi_rresp[1:0]), // Templated + .m_axi_rlast (stub_m_axi_rlast), // Templated + .m_axi_rvalid (stub_m_axi_rvalid)); // Templated + + //###################################################################### + //AXI SLAVE PORT FOR MEMORY + //###################################################################### + + /*esaxi AUTO_TEMPLATE ( + .s_\(.*\) (elink1_m_\1[]), + .\(.*\) (elink1_\1[]), + .\(.*\) (elink1_\1[]), + + ); + */ + + esaxi #(.S_IDW(S_IDW)) esaxi (.s_axi_aclk (clk), + .s_axi_aresetn (nreset), + .s_axi_wstrb ( elink1_m_axi_wstrb[3:0] | elink1_m_axi_wstrb[7:4] ), + /*AUTOINST*/ + // Outputs + .txwr_access (elink1_txwr_access), // Templated + .txwr_packet (elink1_txwr_packet[PW-1:0]), // Templated + .txrd_access (elink1_txrd_access), // Templated + .txrd_packet (elink1_txrd_packet[PW-1:0]), // Templated + .rxrr_wait (elink1_rxrr_wait), // Templated + .s_axi_arready (elink1_m_axi_arready), // Templated + .s_axi_awready (elink1_m_axi_awready), // Templated + .s_axi_bid (elink1_m_axi_bid[S_IDW-1:0]), // Templated + .s_axi_bresp (elink1_m_axi_bresp[1:0]), // Templated + .s_axi_bvalid (elink1_m_axi_bvalid), // Templated + .s_axi_rid (elink1_m_axi_rid[S_IDW-1:0]), // Templated + .s_axi_rdata (elink1_m_axi_rdata[31:0]), // Templated + .s_axi_rlast (elink1_m_axi_rlast), // Templated + .s_axi_rresp (elink1_m_axi_rresp[1:0]), // Templated + .s_axi_rvalid (elink1_m_axi_rvalid), // Templated + .s_axi_wready (elink1_m_axi_wready), // Templated + // Inputs + .txwr_wait (elink1_txwr_wait), // Templated + .txrd_wait (elink1_txrd_wait), // Templated + .rxrr_access (elink1_rxrr_access), // Templated + .rxrr_packet (elink1_rxrr_packet[PW-1:0]), // Templated + .s_axi_arid (elink1_m_axi_arid[S_IDW-1:0]), // Templated + .s_axi_araddr (elink1_m_axi_araddr[31:0]), // Templated + .s_axi_arburst (elink1_m_axi_arburst[1:0]), // Templated + .s_axi_arcache (elink1_m_axi_arcache[3:0]), // Templated + .s_axi_arlock (elink1_m_axi_arlock), // Templated + .s_axi_arlen (elink1_m_axi_arlen[7:0]), // Templated + .s_axi_arprot (elink1_m_axi_arprot[2:0]), // Templated + .s_axi_arqos (elink1_m_axi_arqos[3:0]), // Templated + .s_axi_arsize (elink1_m_axi_arsize[2:0]), // Templated + .s_axi_arvalid (elink1_m_axi_arvalid), // Templated + .s_axi_awid (elink1_m_axi_awid[S_IDW-1:0]), // Templated + .s_axi_awaddr (elink1_m_axi_awaddr[31:0]), // Templated + .s_axi_awburst (elink1_m_axi_awburst[1:0]), // Templated + .s_axi_awcache (elink1_m_axi_awcache[3:0]), // Templated + .s_axi_awlock (elink1_m_axi_awlock), // Templated + .s_axi_awlen (elink1_m_axi_awlen[7:0]), // Templated + .s_axi_awprot (elink1_m_axi_awprot[2:0]), // Templated + .s_axi_awqos (elink1_m_axi_awqos[3:0]), // Templated + .s_axi_awsize (elink1_m_axi_awsize[2:0]), // Templated + .s_axi_awvalid (elink1_m_axi_awvalid), // Templated + .s_axi_bready (elink1_m_axi_bready), // Templated + .s_axi_rready (elink1_m_axi_rready), // Templated + .s_axi_wid (elink1_m_axi_wid[S_IDW-1:0]), // Templated + .s_axi_wdata (elink1_m_axi_wdata[31:0]), // Templated + .s_axi_wlast (elink1_m_axi_wlast), // Templated + .s_axi_wvalid (elink1_m_axi_wvalid)); // Templated + + /*etx_fifo AUTO_TEMPLATE ( + .\(.*\)_fifo_\(.*\) (emem_\1_\2[]), + .\(.*\) (elink1_\1[]), + + ); + */ + + etx_fifo etx_fifo (.sys_nreset (nreset), + .sys_clk (clk), + .tx_lclk_div4 (clk), + .txrd_fifo_wait (emem_txrd_wait), + .txrr_fifo_wait (emem_txrr_wait), + .txwr_fifo_wait (emem_txwr_wait), + /*AUTOINST*/ + // Outputs + .txrd_wait (elink1_txrd_wait), // Templated + .txwr_wait (elink1_txwr_wait), // Templated + .txrr_wait (elink1_txrr_wait), // Templated + .txrd_fifo_access (emem_txrd_access), // Templated + .txrd_fifo_packet (emem_txrd_packet[PW-1:0]), // Templated + .txrr_fifo_access (emem_txrr_access), // Templated + .txrr_fifo_packet (emem_txrr_packet[PW-1:0]), // Templated + .txwr_fifo_access (emem_txwr_access), // Templated + .txwr_fifo_packet (emem_txwr_packet[PW-1:0]), // Templated + // Inputs + .txrd_access (elink1_txrd_access), // Templated + .txrd_packet (elink1_txrd_packet[PW-1:0]), // Templated + .txwr_access (elink1_txwr_access), // Templated + .txwr_packet (elink1_txwr_packet[PW-1:0]), // Templated + .txrr_access (elink1_txrr_access), // Templated + .txrr_packet (elink1_txrr_packet[PW-1:0])); // Templated + //###################################################################### + //AXI SLAVE PORT FOR MEMORY + //###################################################################### + //"Arbitration" between read/write transaction - assign emem_access = ~elink1_rxwr_wait & (elink1_rxwr_access | elink1_rxrd_access); + assign emem_access = emem_txwr_access | emem_txrd_access; - assign emem_packet[PW-1:0] = elink1_rxwr_access ? elink1_rxwr_packet[PW-1:0]: - elink1_rxrd_packet[PW-1:0]; + assign emem_packet[PW-1:0] = emem_txwr_access ? emem_txwr_packet[PW-1:0]: + emem_txrd_packet[PW-1:0]; - assign elink1_rxrd_wait = emem_wait | - elink1_rxwr_access | - elink1_rxwr_wait; + //HACK! + assign emem_txrd_wait = (emem_wait & emem_txrd_access) | emem_txwr_access; + assign emem_txwr_wait = (emem_wait & emem_txwr_access); /*ememory AUTO_TEMPLATE ( - // Outputs - .\(.*\)_out (elink1_txrr_\1[]), + // Outputsd + .\(.*\)_out (elink1_rxrr_\1[]), .\(.*\)_in (emem_\1[]), .wait_out (emem_wait), - .reset (~nreset), ); */ - ememory emem (.wait_in (elink1_txrr_wait),//pushback on reads + ememory emem (.wait_in (elink1_rxrr_wait),//pushback on reads .clk (clk), .wait_out (emem_wait), .coreid (12'h0), /*AUTOINST*/ // Outputs - .access_out (elink1_txrr_access), // Templated - .packet_out (elink1_txrr_packet[PW-1:0]), // Templated + .access_out (elink1_rxrr_access), // Templated + .packet_out (elink1_rxrr_packet[PW-1:0]), // Templated // Inputs .nreset (nreset), .access_in (emem_access), // Templated .packet_in (emem_packet[PW-1:0])); // Templated - - //Write wait circuit - reg [7:0] wait_counter; - always @ (posedge clk or negedge nreset) - if(!nreset) - wait_counter[7:0] <= 'b0; - else - wait_counter[7:0] <= wait_counter+1'b1; - - assign elink1_rxwr_wait = (|wait_counter[4:0]);//(|wait_counter[3:0]);//1'b0; - - endmodule // dv_elink // Local Variables: -// verilog-library-directories:("." "../hdl" "../../emesh/dv" "../../emesh/hdl" "../../memory/hdl") +// verilog-library-directories:("." "../hdl" "../../emesh/dv" "../../axi/dv" "../../emesh/hdl" "../../memory/hdl") // End: diff --git a/elink/dv/dut_elink.v b/elink/dv/dut_elink.v index 21ae850..f2489e4 100644 --- a/elink/dv/dut_elink.v +++ b/elink/dv/dut_elink.v @@ -131,8 +131,6 @@ module dut(/*AUTOARG*/ .c2e_\(.*\)_wait_out(), ); */ - - emesh_if #(.PW(PW)) emesh_if (.c2e_rmesh_access_in(1'b0), .c2e_rmesh_packet_in({(PW){1'b0}}), @@ -141,7 +139,7 @@ module dut(/*AUTOARG*/ .e2c_xmesh_wait_in(1'b0), .e2c_xmesh_access_out(), .e2c_xmesh_packet_out(), - /*AUTOINST*/ + /*AUTOINST*/ // Outputs .c2e_cmesh_wait_out (), // Templated .e2c_cmesh_access_out (elink0_txwr_access), // Templated @@ -333,13 +331,13 @@ module dut(/*AUTOARG*/ .clk (clk), .wait_out (emem_wait), .coreid (12'h0), - .access_in (emem_access), /*AUTOINST*/ // Outputs .access_out (elink1_txrr_access), // Templated .packet_out (elink1_txrr_packet[PW-1:0]), // Templated // Inputs .nreset (nreset), + .access_in (emem_access), // Templated .packet_in (emem_packet[PW-1:0])); // Templated