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Adding SPI module
-Work in progress!
This commit is contained in:
Andreas Olofsson
parent
3c34ba0daa
commit
cbb2ba0279
8
spi/dv/build.sh
Executable file
8
spi/dv/build.sh
Executable file
@ -0,0 +1,8 @@
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#!/bin/bash
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dut="spi"
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top="../../common/dv/dv_top.v"
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iverilog -g2005 -DTARGET_SIM=1 -DTARGET_XILINX=1 $top dut_${dut}.v -f ../../common/dv/libs.cmd -o ${dut}.vvp $1
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#-pfileline=1
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#-Wall
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102
spi/dv/dut_spi.v
Normal file
102
spi/dv/dut_spi.v
Normal file
@ -0,0 +1,102 @@
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module dut(/*AUTOARG*/
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// Outputs
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dut_active, wait_out, access_out, packet_out,
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// Inputs
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clk, nreset, vdd, vss, access_in, packet_in, wait_in
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);
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parameter AW = 32;
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parameter DW = 32;
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parameter CW = 2;
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parameter IDW = 12;
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parameter M_IDW = 6;
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parameter S_IDW = 12;
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parameter PW = 104;
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parameter N = 1;
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//#######################################
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//# CLOCK AND RESET
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//#######################################
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input clk;
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input nreset;
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input [N*N-1:0] vdd;
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input vss;
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output dut_active;
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//#######################################
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//#EMESH INTERFACE
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//#######################################
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//Stimulus Driven Transaction
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input [N-1:0] access_in;
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input [N*PW-1:0] packet_in;
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output [N-1:0] wait_out;
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//DUT driven transactoin
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output [N-1:0] access_out;
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output [N*PW-1:0] packet_out;
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input [N-1:0] wait_in;
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/*AUTOINPUT*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire m_miso; // From spi of spi.v
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wire m_mosi; // From spi of spi.v
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wire m_sclk; // From spi of spi.v
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wire m_ss; // From spi of spi.v
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wire [31:0] reg_rdata; // From spi of spi.v
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wire spi_irq; // From spi of spi.v
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// End of automatics
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wire [AW-1:0] gpio_in; // To gpio of gpio.v
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reg [N-1:0] access_out;
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//######################################################################
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//DUT
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//######################################################################
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assign gpio_in[AW-1:0] = 32'h87654321;
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assign wait_out[N-1:0] = 'b0;
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assign dut_active = 1'b1;
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always @ (posedge clk)
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access_out[0] <= access_in[0] & ~packet_in[0];
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emesh2packet e2p (// Outputs
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.packet_out (packet_out[PW-1:0]),
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// Inputs
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.write_out (1'b0),
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.datamode_out (2'b10),
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.ctrlmode_out (5'b0),
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.dstaddr_out ({(AW){1'b0}}),
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.data_out (reg_rdata[AW-1:0]),
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.srcaddr_out ({(AW){1'b0}})
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);
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/*spi AUTO_TEMPLATE(.s_\(.*\) (m_\1),
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);
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*/
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spi spi (.reg_access (access_in[0]),
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.reg_packet (packet_in[PW-1:0]),
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/*AUTOINST*/
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// Outputs
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.reg_rdata (reg_rdata[31:0]),
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.spi_irq (spi_irq),
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.m_sclk (m_sclk),
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.m_mosi (m_mosi),
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.m_ss (m_ss),
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.s_miso (m_miso), // Templated
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// Inputs
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.nreset (nreset),
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.clk (clk),
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.m_miso (m_miso),
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.s_sclk (m_sclk), // Templated
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.s_mosi (m_mosi), // Templated
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.s_ss (m_ss)); // Templated
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endmodule // dut
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// Local Variables:
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// verilog-library-directories:("." "../hdl" "../../emesh/hdl")
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// End:
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7
spi/dv/run.sh
Executable file
7
spi/dv/run.sh
Executable file
@ -0,0 +1,7 @@
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#!/bin/bash
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if [ -e "test_0.emf" ]
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then
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rm test_0.emf
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fi
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cp $1 test_0.emf
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./spi.vvp
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350
spi/hdl/axi_spi.v
Normal file
350
spi/hdl/axi_spi.v
Normal file
@ -0,0 +1,350 @@
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//########################################################
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// SPI + AXI_SLAVE + AXI_MASTER
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//########################################################
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`include "spi_regmap.v"
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module axi_spi(/*AUTOARG*/
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// Outputs
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txwr_packet, txwr_access, txrr_packet, txrr_access, txrd_packet,
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txrd_access, s_ss, s_mosi, s_mclk, rxwr_wait, rxrr_wait, rxrd_wait,
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m_miso, ss_sel, m_axi_awid, m_axi_awaddr, m_axi_awlen,
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m_axi_awsize, m_axi_awburst, m_axi_awlock, m_axi_awcache,
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m_axi_awprot, m_axi_awqos, m_axi_awvalid, m_axi_wid, m_axi_wdata,
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m_axi_wstrb, m_axi_wlast, m_axi_wvalid, m_axi_bready, m_axi_arid,
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m_axi_araddr, m_axi_arlen, m_axi_arsize, m_axi_arburst,
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m_axi_arlock, m_axi_arcache, m_axi_arprot, m_axi_arqos,
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m_axi_arvalid, m_axi_rready, s_axi_arready, s_axi_awready,
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s_axi_bid, s_axi_bresp, s_axi_bvalid, s_axi_rid, s_axi_rdata,
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s_axi_rlast, s_axi_rresp, s_axi_rvalid, s_axi_wready,
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// Inouts
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miso, mosi, ss, sclk,
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// Inputs
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txwr_wait, txrr_wait, txrd_wait, s_miso, rxwr_packet, rxwr_access,
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rxrr_packet, rxrr_access, rxrd_packet, rxrd_access, m_ss,
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sys_nreset, sys_clk, m_axi_aresetn, m_axi_awready, m_axi_wready,
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m_axi_bid, m_axi_bresp, m_axi_bvalid, m_axi_arready, m_axi_rid,
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m_axi_rdata, m_axi_rresp, m_axi_rlast, m_axi_rvalid, s_axi_aresetn,
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s_axi_arid, s_axi_araddr, s_axi_arburst, s_axi_arcache,
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s_axi_arlock, s_axi_arlen, s_axi_arprot, s_axi_arqos, s_axi_arsize,
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s_axi_arvalid, s_axi_awid, s_axi_awaddr, s_axi_awburst,
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s_axi_awcache, s_axi_awlock, s_axi_awlen, s_axi_awprot,
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s_axi_awqos, s_axi_awsize, s_axi_awvalid, s_axi_bready,
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s_axi_rready, s_axi_wid, s_axi_wdata, s_axi_wlast, s_axi_wstrb,
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s_axi_wvalid
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);
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//########################################################
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// INTERFACE
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//########################################################
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parameter AW = 32; // address width
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parameter PW = 2*AW+40; // packet width
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parameter ID = 12'h810; // addr[31:20] id
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parameter S_IDW = 12; // ID width for S_AXI
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parameter M_IDW = 6; // ID width for M_AXI
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parameter N = 1
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//clk, reset
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input sys_nreset; // active low async reset
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input sys_clk; // system clock for AXI
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//spi interface
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inout miso; // master input / slave output
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inout mosi; // master output / slave input
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inout ss; // slave select (primary)
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inout sclk; // serial clock
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output [N-1:0] ss_sel; // master driven slave selects
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//AXI master
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input m_axi_aresetn; // global reset singal.
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output [M_IDW-1:0] m_axi_awid; // write address ID
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output [31 : 0] m_axi_awaddr; // master interface write address
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output [7 : 0] m_axi_awlen; // burst length.
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output [2 : 0] m_axi_awsize; // burst size.
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output [1 : 0] m_axi_awburst; // burst type.
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output m_axi_awlock; // lock type
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output [3 : 0] m_axi_awcache; // memory type.
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output [2 : 0] m_axi_awprot; // protection type.
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output [3 : 0] m_axi_awqos; // quality of service
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output m_axi_awvalid; // write address valid
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input m_axi_awready; // write address ready
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output [M_IDW-1:0] m_axi_wid;
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output [63 : 0] m_axi_wdata; // master interface write data.
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output [7 : 0] m_axi_wstrb; // byte write strobes
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output m_axi_wlast; // last transfer in a write burst.
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output m_axi_wvalid; // indicates data is ready to go
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input m_axi_wready; // slave is ready for data
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input [M_IDW-1:0] m_axi_bid;
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input [1 : 0] m_axi_bresp; // status of the write transaction.
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input m_axi_bvalid; // valid write response
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output m_axi_bready; // master can accept write response.
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output [M_IDW-1:0] m_axi_arid; // read address ID
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output [31 : 0] m_axi_araddr; // initial address of a read burst
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output [7 : 0] m_axi_arlen; // burst length
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output [2 : 0] m_axi_arsize; // burst size
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output [1 : 0] m_axi_arburst; // burst type
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output m_axi_arlock; // lock type
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output [3 : 0] m_axi_arcache; // memory type
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output [2 : 0] m_axi_arprot; // protection type
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output [3 : 0] m_axi_arqos; // --
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output m_axi_arvalid; // read address and control is valid
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input m_axi_arready; // slave is ready to accept an address
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input [M_IDW-1:0] m_axi_rid;
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input [63 : 0] m_axi_rdata; // master read data
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input [1 : 0] m_axi_rresp; // status of the read transfer
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input m_axi_rlast; // signals last transfer in a read burst
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input m_axi_rvalid; // signaling the required read data
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output m_axi_rready; // master can accept the readback data
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//AXI slave
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input s_axi_aresetn;
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input [S_IDW-1:0] s_axi_arid; //write address ID
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input [31:0] s_axi_araddr;
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input [1:0] s_axi_arburst;
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input [3:0] s_axi_arcache;
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input s_axi_arlock;
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input [7:0] s_axi_arlen;
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input [2:0] s_axi_arprot;
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input [3:0] s_axi_arqos;
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output s_axi_arready;
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input [2:0] s_axi_arsize;
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input s_axi_arvalid;
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input [S_IDW-1:0] s_axi_awid; //write address ID
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input [31:0] s_axi_awaddr;
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input [1:0] s_axi_awburst;
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input [3:0] s_axi_awcache;
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input s_axi_awlock;
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input [7:0] s_axi_awlen;
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input [2:0] s_axi_awprot;
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input [3:0] s_axi_awqos;
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input [2:0] s_axi_awsize;
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input s_axi_awvalid;
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output s_axi_awready;
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output [S_IDW-1:0] s_axi_bid; //write address ID
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output [1:0] s_axi_bresp;
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output s_axi_bvalid;
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input s_axi_bready;
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output [S_IDW-1:0] s_axi_rid; //write address ID
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output [31:0] s_axi_rdata;
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output s_axi_rlast;
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output [1:0] s_axi_rresp;
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output s_axi_rvalid;
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input s_axi_rready;
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input [S_IDW-1:0] s_axi_wid; //write address ID
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input [31:0] s_axi_wdata;
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input s_axi_wlast;
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input [3:0] s_axi_wstrb;
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input s_axi_wvalid;
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output s_axi_wready;
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//########################################################
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// BODY
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//########################################################
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/*AUTOINPUT*/
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// Beginning of automatic inputs (from unused autoinst inputs)
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input [N-1:0] m_ss; // To spi of spi.v, ...
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input rxrd_access; // To emaxi of emaxi.v
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input [PW-1:0] rxrd_packet; // To emaxi of emaxi.v
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input rxrr_access; // To esaxi of esaxi.v
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input [PW-1:0] rxrr_packet; // To esaxi of esaxi.v
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input rxwr_access; // To emaxi of emaxi.v
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input [PW-1:0] rxwr_packet; // To emaxi of emaxi.v
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input s_miso; // To spi of spi.v, ...
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input txrd_wait; // To esaxi of esaxi.v
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input txrr_wait; // To emaxi of emaxi.v
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input txwr_wait; // To esaxi of esaxi.v
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// End of automatics
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/*AUTOOUTPUT*/
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// Beginning of automatic outputs (from unused autoinst outputs)
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output m_miso; // From spi of spi.v, ...
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output rxrd_wait; // From emaxi of emaxi.v
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output rxrr_wait; // From esaxi of esaxi.v
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output rxwr_wait; // From emaxi of emaxi.v
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output s_mclk; // From spi of spi.v, ...
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output s_mosi; // From spi of spi.v, ...
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output s_ss; // From spi of spi.v, ...
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output txrd_access; // From esaxi of esaxi.v
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output [PW-1:0] txrd_packet; // From esaxi of esaxi.v
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output txrr_access; // From emaxi of emaxi.v
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output [PW-1:0] txrr_packet; // From emaxi of emaxi.v
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output txwr_access; // From esaxi of esaxi.v
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output [PW-1:0] txwr_packet; // From esaxi of esaxi.v
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// End of automatics
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// End of automatics
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire m_mclk; // From spi of spi.v
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wire m_mosi; // From spi of spi.v
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// End of automatics
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//########################################################
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//SPI
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//########################################################
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//SPI Logic
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spi spi(/*AUTOINST*/
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// Outputs
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.m_mclk (m_mclk),
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.m_mosi (m_mosi),
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.m_miso (m_miso),
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.s_mclk (s_mclk),
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.s_mosi (s_mosi),
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.s_ss (s_ss),
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// Inputs
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.m_ss (m_ss[N-1:0]),
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.s_miso (s_miso));
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//IO cells
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spi_io spi_io (/*AUTOINST*/
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// Outputs
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.ss_sel (ss_sel[N-2:0]),
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.m_miso (m_miso),
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.s_mclk (s_mclk),
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.s_mosi (s_mosi),
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.s_ss (s_ss),
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// Inouts
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.sclk (sclk),
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.mosi (mosi),
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.miso (miso),
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.ss (ss),
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// Inputs
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.m_mclk (m_mclk),
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.m_mosi (m_mosi),
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.m_ss (m_ss[N-1:0]),
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.s_miso (s_miso));
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//########################################################
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//AXI SLAVE
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//########################################################
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/*esaxi AUTO_TEMPLATE (//Stimulus
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.rr_\(.*\) (rxrr_\1[]),
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.rd_\(.*\) (txrd_\1[]),
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.wr_\(.*\) (txwr_\1[]),
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);
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*/
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esaxi #(.S_IDW(S_IDW),
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.RETURN_ADDR(RETURN_ADDR))
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esaxi (.s_axi_aclk (sys_clk),
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/*AUTOINST*/
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// Outputs
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.wr_access (txwr_access), // Templated
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.wr_packet (txwr_packet[PW-1:0]), // Templated
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.rd_access (txrd_access), // Templated
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.rd_packet (txrd_packet[PW-1:0]), // Templated
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.rr_wait (rxrr_wait), // Templated
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.s_axi_arready (s_axi_arready),
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.s_axi_awready (s_axi_awready),
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.s_axi_bid (s_axi_bid[S_IDW-1:0]),
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.s_axi_bresp (s_axi_bresp[1:0]),
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.s_axi_bvalid (s_axi_bvalid),
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.s_axi_rid (s_axi_rid[S_IDW-1:0]),
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.s_axi_rdata (s_axi_rdata[31:0]),
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.s_axi_rlast (s_axi_rlast),
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.s_axi_rresp (s_axi_rresp[1:0]),
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.s_axi_rvalid (s_axi_rvalid),
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.s_axi_wready (s_axi_wready),
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// Inputs
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.wr_wait (txwr_wait), // Templated
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.rd_wait (txrd_wait), // Templated
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.rr_access (rxrr_access), // Templated
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.rr_packet (rxrr_packet[PW-1:0]), // Templated
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.s_axi_aresetn (s_axi_aresetn),
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.s_axi_arid (s_axi_arid[S_IDW-1:0]),
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.s_axi_araddr (s_axi_araddr[31:0]),
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.s_axi_arburst (s_axi_arburst[1:0]),
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||||
.s_axi_arcache (s_axi_arcache[3:0]),
|
||||
.s_axi_arlock (s_axi_arlock),
|
||||
.s_axi_arlen (s_axi_arlen[7:0]),
|
||||
.s_axi_arprot (s_axi_arprot[2:0]),
|
||||
.s_axi_arqos (s_axi_arqos[3:0]),
|
||||
.s_axi_arsize (s_axi_arsize[2:0]),
|
||||
.s_axi_arvalid (s_axi_arvalid),
|
||||
.s_axi_awid (s_axi_awid[S_IDW-1:0]),
|
||||
.s_axi_awaddr (s_axi_awaddr[31:0]),
|
||||
.s_axi_awburst (s_axi_awburst[1:0]),
|
||||
.s_axi_awcache (s_axi_awcache[3:0]),
|
||||
.s_axi_awlock (s_axi_awlock),
|
||||
.s_axi_awlen (s_axi_awlen[7:0]),
|
||||
.s_axi_awprot (s_axi_awprot[2:0]),
|
||||
.s_axi_awqos (s_axi_awqos[3:0]),
|
||||
.s_axi_awsize (s_axi_awsize[2:0]),
|
||||
.s_axi_awvalid (s_axi_awvalid),
|
||||
.s_axi_bready (s_axi_bready),
|
||||
.s_axi_rready (s_axi_rready),
|
||||
.s_axi_wid (s_axi_wid[S_IDW-1:0]),
|
||||
.s_axi_wdata (s_axi_wdata[31:0]),
|
||||
.s_axi_wlast (s_axi_wlast),
|
||||
.s_axi_wstrb (s_axi_wstrb[3:0]),
|
||||
.s_axi_wvalid (s_axi_wvalid));
|
||||
|
||||
//########################################################
|
||||
//AXI MASTER INTERFACE
|
||||
//########################################################
|
||||
/*emaxi AUTO_TEMPLATE (//Stimulus
|
||||
.rr_\(.*\) (txrr_\1[]),
|
||||
.rd_\(.*\) (rxrd_\1[]),
|
||||
.wr_\(.*\) (rxwr_\1[]),
|
||||
);
|
||||
*/
|
||||
emaxi #(.M_IDW(M_IDW))
|
||||
emaxi (.m_axi_aclk (sys_clk),
|
||||
/*AUTOINST*/
|
||||
// Outputs
|
||||
.wr_wait (rxwr_wait), // Templated
|
||||
.rd_wait (rxrd_wait), // Templated
|
||||
.rr_access (txrr_access), // Templated
|
||||
.rr_packet (txrr_packet[PW-1:0]), // Templated
|
||||
.m_axi_awid (m_axi_awid[M_IDW-1:0]),
|
||||
.m_axi_awaddr (m_axi_awaddr[31:0]),
|
||||
.m_axi_awlen (m_axi_awlen[7:0]),
|
||||
.m_axi_awsize (m_axi_awsize[2:0]),
|
||||
.m_axi_awburst (m_axi_awburst[1:0]),
|
||||
.m_axi_awlock (m_axi_awlock),
|
||||
.m_axi_awcache (m_axi_awcache[3:0]),
|
||||
.m_axi_awprot (m_axi_awprot[2:0]),
|
||||
.m_axi_awqos (m_axi_awqos[3:0]),
|
||||
.m_axi_awvalid (m_axi_awvalid),
|
||||
.m_axi_wid (m_axi_wid[M_IDW-1:0]),
|
||||
.m_axi_wdata (m_axi_wdata[63:0]),
|
||||
.m_axi_wstrb (m_axi_wstrb[7:0]),
|
||||
.m_axi_wlast (m_axi_wlast),
|
||||
.m_axi_wvalid (m_axi_wvalid),
|
||||
.m_axi_bready (m_axi_bready),
|
||||
.m_axi_arid (m_axi_arid[M_IDW-1:0]),
|
||||
.m_axi_araddr (m_axi_araddr[31:0]),
|
||||
.m_axi_arlen (m_axi_arlen[7:0]),
|
||||
.m_axi_arsize (m_axi_arsize[2:0]),
|
||||
.m_axi_arburst (m_axi_arburst[1:0]),
|
||||
.m_axi_arlock (m_axi_arlock),
|
||||
.m_axi_arcache (m_axi_arcache[3:0]),
|
||||
.m_axi_arprot (m_axi_arprot[2:0]),
|
||||
.m_axi_arqos (m_axi_arqos[3:0]),
|
||||
.m_axi_arvalid (m_axi_arvalid),
|
||||
.m_axi_rready (m_axi_rready),
|
||||
// Inputs
|
||||
.wr_access (rxwr_access), // Templated
|
||||
.wr_packet (rxwr_packet[PW-1:0]), // Templated
|
||||
.rd_access (rxrd_access), // Templated
|
||||
.rd_packet (rxrd_packet[PW-1:0]), // Templated
|
||||
.rr_wait (txrr_wait), // Templated
|
||||
.m_axi_aresetn (m_axi_aresetn),
|
||||
.m_axi_awready (m_axi_awready),
|
||||
.m_axi_wready (m_axi_wready),
|
||||
.m_axi_bid (m_axi_bid[M_IDW-1:0]),
|
||||
.m_axi_bresp (m_axi_bresp[1:0]),
|
||||
.m_axi_bvalid (m_axi_bvalid),
|
||||
.m_axi_arready (m_axi_arready),
|
||||
.m_axi_rid (m_axi_rid[M_IDW-1:0]),
|
||||
.m_axi_rdata (m_axi_rdata[63:0]),
|
||||
.m_axi_rresp (m_axi_rresp[1:0]),
|
||||
.m_axi_rlast (m_axi_rlast),
|
||||
.m_axi_rvalid (m_axi_rvalid));
|
||||
|
||||
|
||||
endmodule // elink
|
||||
// Local Variables:
|
||||
// verilog-library-directories:("." "../../axi/hdl")
|
||||
// End:
|
||||
|
||||
108
spi/hdl/spi.v
Normal file
108
spi/hdl/spi.v
Normal file
@ -0,0 +1,108 @@
|
||||
//# REFERENCE:
|
||||
//# [0] https://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus
|
||||
//# [1] http://www.nxp.com/files/microcontrollers/doc/ref_manual/M68HC11RM.pdf
|
||||
//# [2] http://www.atmel.com/images/doc32017.pdf
|
||||
//# [3] https://www.adafruit.com/datasheets/1897_datasheet.pdf
|
||||
//# [4] https://www.analog.com/media/en/technical-documentation/application-notes/56755538964965031881813AN_877.pdf?doc=AD9652.pdf
|
||||
|
||||
module spi (/*AUTOARG*/
|
||||
// Outputs
|
||||
reg_rdata, spi_irq, m_sclk, m_mosi, m_ss, s_miso,
|
||||
// Inputs
|
||||
nreset, clk, reg_access, reg_packet, m_miso, s_sclk, s_mosi, s_ss
|
||||
);
|
||||
|
||||
//##################################################################
|
||||
//# INTERFACE
|
||||
//##################################################################
|
||||
|
||||
parameter AW = 32; // data width of fifo
|
||||
parameter PW = 2*AW+40; // packet size
|
||||
parameter DEPTH = 32; // fifo depth
|
||||
|
||||
//clk+reset
|
||||
input nreset; // asynchronous active low reset
|
||||
input clk; // write clock
|
||||
|
||||
//register access
|
||||
input reg_access; // register access (read only)
|
||||
input [PW-1:0] reg_packet; // data/address
|
||||
output [31:0] reg_rdata; // readback data
|
||||
|
||||
//interrupt
|
||||
output spi_irq; // interrupt output
|
||||
|
||||
//master spi
|
||||
output m_sclk; // master clock
|
||||
output m_mosi; // master output
|
||||
output m_ss; // slave select
|
||||
input m_miso; // master input
|
||||
|
||||
//slave spi
|
||||
input s_sclk; // slave clock
|
||||
input s_mosi; // slave input
|
||||
input s_ss; // slave select
|
||||
output s_miso; // slave output
|
||||
|
||||
//##################################################################
|
||||
//# BODY
|
||||
//##################################################################
|
||||
|
||||
/*AUTOINPUT*/
|
||||
|
||||
/*AUTOWIRE*/
|
||||
// Beginning of automatic wires (for undeclared instantiated-module outputs)
|
||||
wire access; // From spi_rx of spi_rx.v
|
||||
wire cpha; // From spi_regs of spi_regs.v
|
||||
wire cpol; // From spi_regs of spi_regs.v
|
||||
wire miso; // From spi_tx of spi_tx.v
|
||||
wire mosi; // From spi_tx of spi_tx.v
|
||||
wire [7:0] rxdata; // From spi_rx of spi_rx.v
|
||||
wire sclk; // From spi_tx of spi_tx.v
|
||||
wire ss; // From spi_tx of spi_tx.v
|
||||
wire [7:0] txdata; // From spi_regs of spi_regs.v
|
||||
// End of automatics
|
||||
|
||||
spi_regs spi_regs (/*AUTOINST*/
|
||||
// Outputs
|
||||
.reg_rdata (reg_rdata[31:0]),
|
||||
.cpol (cpol),
|
||||
.cpha (cpha),
|
||||
.txdata (txdata[7:0]),
|
||||
// Inputs
|
||||
.nreset (nreset),
|
||||
.clk (clk),
|
||||
.reg_access (reg_access),
|
||||
.reg_packet (reg_packet[PW-1:0]),
|
||||
.rxdata (rxdata[7:0]));
|
||||
|
||||
spi_tx spi_tx (/*AUTOINST*/
|
||||
// Outputs
|
||||
.sclk (sclk),
|
||||
.mosi (mosi),
|
||||
.miso (miso),
|
||||
.ss (ss),
|
||||
// Inputs
|
||||
.nreset (nreset),
|
||||
.clk (clk),
|
||||
.access (access),
|
||||
.txdata (txdata[7:0]),
|
||||
.cpol (cpol),
|
||||
.cpha (cpha));
|
||||
|
||||
spi_rx spi_rx (/*AUTOINST*/
|
||||
// Outputs
|
||||
.access (access),
|
||||
.rxdata (rxdata[7:0]),
|
||||
// Inputs
|
||||
.nreset (nreset),
|
||||
.clk (clk),
|
||||
.cpol (cpol),
|
||||
.cpha (cpha),
|
||||
.sclk (sclk),
|
||||
.mosi (mosi),
|
||||
.miso (miso),
|
||||
.ss (ss));
|
||||
|
||||
|
||||
endmodule // spi
|
||||
39
spi/hdl/spi_io.v
Normal file
39
spi/hdl/spi_io.v
Normal file
@ -0,0 +1,39 @@
|
||||
module spi_io(/*AUTOARG*/
|
||||
// Outputs
|
||||
ss_sel,
|
||||
// Inouts
|
||||
sclk, mosi, miso, ss
|
||||
);
|
||||
|
||||
//##############################################################
|
||||
//#INTERFACE
|
||||
//###############################################################
|
||||
parameter N = 1; // number of slave selects supported
|
||||
|
||||
//SPI IO interface
|
||||
inout sclk; // serial clk
|
||||
inout mosi; // master output / slave input
|
||||
inout miso; // master input / slave output
|
||||
inout ss; // primary slave select master/slave
|
||||
output [N-2:0] ss_sel; // extra slave selects in master mode
|
||||
|
||||
//master side
|
||||
input m_mclk; //master clock
|
||||
input m_mosi; //master output
|
||||
input [N-1:0] m_ss; //slave select
|
||||
output m_miso; //master input
|
||||
|
||||
//slave side
|
||||
output s_mclk; //slave clock
|
||||
output s_mosi; //slave input
|
||||
output s_ss; //slave select
|
||||
input s_miso; //slave output
|
||||
|
||||
//place IO buffers
|
||||
|
||||
|
||||
|
||||
endmodule // spi_io
|
||||
|
||||
|
||||
|
||||
13
spi/hdl/spi_regmap.v
Normal file
13
spi/hdl/spi_regmap.v
Normal file
@ -0,0 +1,13 @@
|
||||
`ifndef GPIO_REGMAP_V_
|
||||
`define GPIO_REGMAP_V_
|
||||
|
||||
`define SPI_CFG 6'h0
|
||||
`define SPI_STATUS 6'h1
|
||||
`define SPI_ILAT 6'h2
|
||||
`define SPI_IMASK 6'h3
|
||||
`define SPI_DELAY 6'h4
|
||||
`define SPI_TX 6'h5
|
||||
`define SPI_RX 6'h6
|
||||
|
||||
`endif // `ifndef GPIO_REGMAP_V_
|
||||
|
||||
53
spi/hdl/spi_regs.v
Normal file
53
spi/hdl/spi_regs.v
Normal file
@ -0,0 +1,53 @@
|
||||
`include "spi_regmap.v"
|
||||
module spi_regs (/*AUTOARG*/
|
||||
// Outputs
|
||||
reg_rdata, cpol, cpha, txdata,
|
||||
// Inputs
|
||||
nreset, clk, reg_access, reg_packet, rxdata
|
||||
);
|
||||
|
||||
//##################################################################
|
||||
//# INTERFACE
|
||||
//##################################################################
|
||||
|
||||
parameter AW = 32; // data width of fifo
|
||||
parameter PW = 2*AW+40; // packet size
|
||||
parameter DEPTH = 32; // fifo depth
|
||||
|
||||
//clk+reset
|
||||
input nreset; // asynchronous active low reset
|
||||
input clk; // write clock
|
||||
|
||||
//register access
|
||||
input reg_access; // register access (read only)
|
||||
input [PW-1:0] reg_packet; // data/address
|
||||
output [31:0] reg_rdata; // readback data
|
||||
|
||||
//controls
|
||||
output cpol;
|
||||
output cpha;
|
||||
|
||||
//io interface
|
||||
output [7:0] txdata; // data in txfifo
|
||||
input [7:0] rxdata; // data for rxfifo
|
||||
|
||||
|
||||
|
||||
//##################################################################
|
||||
//# BODY
|
||||
//##################################################################
|
||||
|
||||
reg [31:0] status_reg;
|
||||
reg [31:0] config_reg;
|
||||
reg [31:0] ilat_reg;
|
||||
reg [31:0] imask_reg;
|
||||
reg [31:0] delay_reg;
|
||||
reg [31:0] tx_reg;
|
||||
reg [31:0] rx_reg;
|
||||
|
||||
|
||||
|
||||
|
||||
endmodule // spi_regs
|
||||
|
||||
|
||||
39
spi/hdl/spi_rx.v
Normal file
39
spi/hdl/spi_rx.v
Normal file
@ -0,0 +1,39 @@
|
||||
module spi_rx(/*AUTOARG*/
|
||||
// Outputs
|
||||
access, rxdata,
|
||||
// Inputs
|
||||
nreset, clk, cpol, cpha, sclk, mosi, miso, ss
|
||||
);
|
||||
|
||||
//##############################################################
|
||||
//#INTERFACE
|
||||
//###############################################################
|
||||
|
||||
//clk,reset
|
||||
input nreset; // async active low reset
|
||||
input clk; // core clock
|
||||
|
||||
//config
|
||||
input cpol; // clock polarity (0=base value is 0)
|
||||
input cpha; // clock phase (0=sample on first edge)
|
||||
|
||||
//IO interface
|
||||
input sclk; // serial clock
|
||||
input mosi; // slave input (from master)
|
||||
input miso; // slave output (to master)
|
||||
input ss; // slave select
|
||||
|
||||
//data received
|
||||
output access; // write fifo
|
||||
output [7:0] rxdata; // data for fifo
|
||||
// (synchronized to clk)
|
||||
|
||||
//##############################################################
|
||||
//#BODY
|
||||
//###############################################################
|
||||
|
||||
endmodule // spi_rx
|
||||
|
||||
|
||||
|
||||
|
||||
39
spi/hdl/spi_tx.v
Normal file
39
spi/hdl/spi_tx.v
Normal file
@ -0,0 +1,39 @@
|
||||
module spi_tx(/*AUTOARG*/
|
||||
// Outputs
|
||||
sclk, mosi, miso, ss,
|
||||
// Inputs
|
||||
nreset, clk, access, txdata, cpol, cpha
|
||||
);
|
||||
|
||||
//##############################################################
|
||||
//#INTERFACE
|
||||
//###############################################################
|
||||
|
||||
//clk,reset
|
||||
input nreset; // async active low reset
|
||||
input clk; // clock input
|
||||
|
||||
//tx
|
||||
input access; // fifo not empty
|
||||
input [7:0] txdata; // data to transmit on 'mosi'
|
||||
|
||||
//config
|
||||
input cpol; // clock polarity (0=base value is 0)
|
||||
input cpha; // clock phase (0=sample on first edge)
|
||||
|
||||
//serial interface to and from IO
|
||||
output sclk; // serial clock
|
||||
output mosi; // master output
|
||||
output miso; // slave output
|
||||
output ss; // slave select
|
||||
|
||||
//##############################################################
|
||||
//#BODY
|
||||
//###############################################################
|
||||
|
||||
|
||||
|
||||
endmodule // spi_tx
|
||||
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user