diff --git a/elink/hdl/eclocks.v b/elink/hdl/eclocks.v index d1dc560..a8f7776 100644 --- a/elink/hdl/eclocks.v +++ b/elink/hdl/eclocks.v @@ -1,26 +1,21 @@ /*########################################################################### - # Function: High speed clock generator elink module + # Function: High speed clock generator for elink # - # cclk_p/n - Epiphany Core Clock, Differential, must be connected - # directly to IO pins. + # cclk_p/n - Epiphany Output Clock (>600MHz) # - # tx_lclk_par - Parallel data clock, at bit rate / 8 for etx + # tx_lclk_div4 - Parallel data clock (125Mhz) # - # tx_lclk - Serial DDR data clock, at bit rate / 2 for etx + # tx_lclk - Serial DDR data clock (500MHz) # - # tx_lclk_out - DDR "Clock" clock, to generate tx_lclk_p/n output - # At bit rate / 2, 90deg shifted from tx_lclk - # - # Notes: Uses Xilinx macros throughout + # tx_lclk90 - DDR "Clock" clock, to generate tx_lclk_p/n output + # Same as lclk, shifted by 90 degrees # ############################################################################ */ -`timescale 1ns/1ps - module eclocks (/*AUTOARG*/ // Outputs - cclk_p, cclk_n, tx_lclk, tx_lclk_out, tx_lclk_par, + cclk_p, cclk_n, tx_lclk, tx_lclk90, tx_lclk_div4, // Inputs clkin, hard_reset, ecfg_clk_settings, clkbypass ); @@ -30,17 +25,8 @@ module eclocks (/*AUTOARG*/ // VCO frequency = PFD input frequency * CLKFBOUT_MULT (800-1600MHz) // Output frequency = VCO frequency / CLKOUTn_DIVIDE - parameter CLKIN_PERIOD = 10.000; // ns -> 100MHz - parameter CLKIN_DIVIDE = 1; - parameter VCO_MULT = 12; // VCO = 1200MHz - parameter CCLK_DIVIDE = 2; // CCLK = 600MHz - parameter LCLK_DIVIDE = 4; // LCLK = 300MHz (600MB/s eLink) - parameter FEATURE_CCLK_DIV = 1'b1; - parameter IOSTD_ELINK = "LVDS_25"; - parameter INC_PLL = 1; - //Input clock, reset, config interface - input clkin; // primary input clock + input clkin; // primary input clock input hard_reset; // input [15:0] ecfg_clk_settings; // clock settings input [2:0] clkbypass; // for bypassing PLL @@ -49,241 +35,69 @@ module eclocks (/*AUTOARG*/ //Output Clocks output cclk_p, cclk_n; // high speed Epiphany clock (up to 1GHz) output tx_lclk; // elink tx serdes clock - output tx_lclk_out; // center aligned output clock for elink tx - output tx_lclk_par; // lclk/8 slow clock for tx parallel logic + output tx_lclk90; // center aligned output clock for elink tx + output tx_lclk_div4; // lclk/4 slow clock for tx parallel logic // Wires wire cclk_en; wire lclk_en; - - + wire cclk; + //Register decoding assign cclk_en=ecfg_clk_settings[0]; assign lclk_en=ecfg_clk_settings[1]; - -`ifdef TARGET_XILINX - wire clkfb; - wire pll_cclk; //full speed cclk - wire pll_lclk; //full speed lclk etx - wire pll_lclk_out; //full speed lclk for pin for etx - wire pll_lclk_par; //low speed lclk for etx - wire pll_cclk_div; //low speed cclk - wire pll_cclk_standby; //standby clock - wire cclk; - wire cclk_base; - wire cclk_div; - // PLL Primitive -generate - for (i=0; i< INC_PLL; i=i+1) begin : PLL - PLLE2_BASE - #( - .BANDWIDTH("OPTIMIZED"), // OPTIMIZED, HIGH, LOW - .CLKFBOUT_MULT(VCO_MULT), // Multiply value for all CLKOUT, (2-64) - .CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB, (-360.000-360.000). - .CLKIN1_PERIOD(CLKIN_PERIOD),// Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz). - // CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for each CLKOUT (1-128) - .CLKOUT0_DIVIDE(CCLK_DIVIDE), //full speed - .CLKOUT1_DIVIDE(LCLK_DIVIDE), //full speed - .CLKOUT2_DIVIDE(LCLK_DIVIDE), //full speed - .CLKOUT3_DIVIDE(LCLK_DIVIDE * 4), //low speed - .CLKOUT4_DIVIDE(CCLK_DIVIDE * 4), //low speed - .CLKOUT5_DIVIDE(128), //veeery low speed - // CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for each CLKOUT (0.001-0.999). - .CLKOUT0_DUTY_CYCLE(0.5), - .CLKOUT1_DUTY_CYCLE(0.5), - .CLKOUT2_DUTY_CYCLE(0.5), - .CLKOUT3_DUTY_CYCLE(0.5), - .CLKOUT4_DUTY_CYCLE(0.5), - .CLKOUT5_DUTY_CYCLE(0.5), - // CLKOUT0_PHASE - CLKOUT5_PHASE: Phase offset for each CLKOUT (-360.000-360.000). - .CLKOUT0_PHASE(0.0), - .CLKOUT1_PHASE(0.0), - .CLKOUT2_PHASE(90.0), - .CLKOUT3_PHASE(0.0), - .CLKOUT4_PHASE(0.0), - .CLKOUT5_PHASE(0.0), - .DIVCLK_DIVIDE(CLKIN_DIVIDE),// Master division value, (1-56) - .REF_JITTER1(0.01), // Reference input jitter (0.000-0.999). - .STARTUP_WAIT("FALSE") // Delay DONE until PLL Locks, ("TRUE"/"FALSE") - ) eclk_pll - ( - // Clock Outputs: 1-bit (each) output: User configurable clock outputs - .CLKOUT0(pll_cclk), //full speed cclk - .CLKOUT1(pll_lclk), //full speed lclk etx - .CLKOUT2(pll_lclk_out), //full speed lclk for pin for etx - .CLKOUT3(pll_lclk_par), //low speed lclk for etx - .CLKOUT4(pll_cclk_div), //low speed cclk - .CLKOUT5(pll_cclk_standby), //standby clock - .CLKFBOUT(clkfb), //feedback clock output - .LOCKED(), //lock signal - .CLKIN1(clkin), //main input clock - .PWRDWN(1'b0), //pll power down - .RST(1'b0), //reset - .CLKFBIN(clkfb) //feedback clock input - ); - - - //TODO!! Redesign this all together!!! - - // Output buffering - BUFG cclk_buf (.O (cclk_base), .I (pll_cclk)); - BUFG cclk_div_buf (.O (cclk_div), .I (pll_cclk_div)); - BUFG lclk_buf (.O (tx_lclk), .I (pll_lclk)); - BUFG lclk_out_buf (.O (tx_lclk_out), .I (pll_lclk_out)); - BUFG lclk_par_buf (.O (tx_lclk_par), .I (pll_lclk_par)); +`ifdef TARGET_XILINX -generate - if( FEATURE_CCLK_DIV ) begin : gen_cclk_div - - // Create adjustable (but fast) CCLK - wire rxi_cclk_out; - reg [8:1] cclk_pattern; - reg [4:0] clk_div_sync; - reg enb_sync; + //instantiate MMCM - always @ (posedge cclk_div) begin // Might need x-clock TIG here - - clk_div_sync <= {cclk_en,ecfg_clk_settings[7:4]}; - - - if(enb_sync) - case(clk_div_sync) - 4'h0: cclk_pattern <= 8'd0; // Clock OFF - 4'h0: cclk_pattern <= 8'b10101010; // Divide by 1 - 4'h6: cclk_pattern <= 8'b11001100; // Divide by 2 - 4'h5: cclk_pattern <= 8'b11110000; // Divide by 4 - default: cclk_pattern <= {8{~cclk_pattern[1]}}; // /8 - endcase - else - cclk_pattern <= 8'b00000000; - end // always @ (posedge cclk_div) - - - //CCLK CLOCK DIVIDER - OSERDESE2 - #( - .DATA_RATE_OQ("DDR"), // DDR, SDR - .DATA_RATE_TQ("SDR"), // DDR, BUF, SDR - .DATA_WIDTH(8), // Parallel data width (2-8,10,14) - .INIT_OQ(1'b0), // Initial value of OQ output (1'b0,1'b1) - .INIT_TQ(1'b0), // Initial value of TQ output (1'b0,1'b1) - .SERDES_MODE("MASTER"), // MASTER, SLAVE - .SRVAL_OQ(1'b0), // OQ output value when SR is used (1'b0,1'b1) - .SRVAL_TQ(1'b0), // TQ output value when SR is used (1'b0,1'b1) - .TBYTE_CTL("FALSE"), // Enable tristate byte operation (FALSE, TRUE) - .TBYTE_SRC("FALSE"), // Tristate byte source (FALSE, TRUE) - .TRISTATE_WIDTH(1) // 3-state converter width (1,4) - ) OSERDESE2_inst - ( - .OFB(), // Feedback path for data - .OQ(cclk), // Data path output - .SHIFTOUT1(), - .SHIFTOUT2(), - .TBYTEOUT(), // Byte group tristate - .TFB(), // 1-bit output: 3-state control - .TQ(), // 3-state control - .CLK(cclk_base), // High speed clock - .CLKDIV(cclk_div), // Divided clock - .D1(cclk_pattern[1]), // Parallel data inputs - .D2(cclk_pattern[2]), - .D3(cclk_pattern[3]), - .D4(cclk_pattern[4]), - .D5(cclk_pattern[5]), - .D6(cclk_pattern[6]), - .D7(cclk_pattern[7]), - .D8(cclk_pattern[8]), - .OCE(1'b1), // Output data clock enable TODO: gating? - .RST(hard_reset), // Reset - .SHIFTIN1(1'b0), // Data input expansion (1-bit each) - .SHIFTIN2(1'b0), - .T1(1'b0), // Parallel 3-state inputs - .T2(1'b0), - .T3(1'b0), - .T4(1'b0), - .TBYTEIN(1'b0), // Byte group tristate - .TCE(1'b0) // 3-state clock enable - ); - - end else - begin : gen_fixed_cclk // Non-dividable CCLK - reg enb_sync; - - always @ (posedge cclk_div) - enb_sync <= ~(ecfg_clk_settings[3:0]==4'b0000); - - // The following does not result in timing failures, - // but doesn't seem glitch-safe - assign cclk = cclk_base & enb_sync; - end -endgenerate - - //Clock output - OBUFDS #(.IOSTANDARD (IOSTD_ELINK)) obufds_cclk_inst (.O (cclk_p), .OB (cclk_n), .I (cclk)); - - end // block: PLL -endgenerate - `elsif TARGET_CLEAN - wire cclk; - wire lclk_par; - wire lclk; - wire lclk_out; - - + clock_divider cclk_divider( // Outputs .clkout (cclk), .clkout90 (), // Inputs .clkin (clkin), - .reset (hard_reset), + .reset (hard_reset & cclk_en),//glitchy hack .divcfg (ecfg_clk_settings[7:4]) ); - - - assign cclk_p = cclk & cclk_en ; - assign cclk_n = ~cclk_p; clock_divider lclk_divider( // Outputs - .clkout (lclk), - .clkout90 (lclk_out), + .clkout (tx_lclk), + .clkout90 (tx_lclk90), // Inputs .clkin (clkin), - .reset (hard_reset), + .reset (hard_reset & lclk_en),//glitchy hack .divcfg (ecfg_clk_settings[11:8]) ); clock_divider lclk_par_divider( // Outputs - .clkout (lclk_par), + .clkout (tx_lclk_div4), .clkout90 (), // Inputs .clkin (clkin), - .reset (hard_reset), + .reset (hard_reset & lclk_en),//glitchy hack .divcfg (ecfg_clk_settings[11:8] + 4'd2) ); - - //Clock enables - assign tx_lclk_par = lclk_par & lclk_en; - assign tx_lclk = lclk & lclk_en; - assign tx_lclk_out = lclk_out & lclk_en; + //Output buffer + assign cclk_p = cclk & cclk_en ; + assign cclk_n = ~cclk_p; + `endif - - - + endmodule // eclocks // Local Variables: // verilog-library-directories:("." "../../common/hdl") // End: - /* Copyright (C) 2014 Adapteva, Inc. - Contributed by Fred Huettig + Contributed by Andreas Olofsson This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by diff --git a/elink/hdl/elink.v b/elink/hdl/elink.v index 69a458b..0d87035 100644 --- a/elink/hdl/elink.v +++ b/elink/hdl/elink.v @@ -523,8 +523,8 @@ module elink(/*AUTOARG*/ wire reset; // From ereset of ereset.v wire soft_reset; // From ecfg of ecfg.v wire tx_lclk; // From eclocks of eclocks.v - wire tx_lclk_out; // From eclocks of eclocks.v - wire tx_lclk_par; // From eclocks of eclocks.v + wire tx_lclk90; // From eclocks of eclocks.v + wire tx_lclk_div4; // From eclocks of eclocks.v // End of automatics @@ -794,8 +794,8 @@ module elink(/*AUTOARG*/ // Inputs .reset (reset), .tx_lclk (tx_lclk), - .tx_lclk_out (tx_lclk_out), - .tx_lclk_par (tx_lclk_par), + .tx_lclk90 (tx_lclk90), + .tx_lclk_div4 (tx_lclk_div4), .s_axi_aclk (s_axi_aclk), .m_axi_aclk (m_axi_aclk), .ecfg_tx_enable (ecfg_tx_enable), @@ -919,8 +919,8 @@ module elink(/*AUTOARG*/ .cclk_p (cclk_p), .cclk_n (cclk_n), .tx_lclk (tx_lclk), - .tx_lclk_out (tx_lclk_out), - .tx_lclk_par (tx_lclk_par), + .tx_lclk90 (tx_lclk90), + .tx_lclk_div4 (tx_lclk_div4), // Inputs .clkin (clkin), .hard_reset (hard_reset), diff --git a/elink/hdl/etx.v b/elink/hdl/etx.v index ec1265d..0807135 100644 --- a/elink/hdl/etx.v +++ b/elink/hdl/etx.v @@ -4,7 +4,7 @@ module etx(/*AUTOARG*/ emrr_progfull, txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n, txo_data_p, txo_data_n, mi_dout, // Inputs - reset, tx_lclk, tx_lclk_out, tx_lclk_par, s_axi_aclk, m_axi_aclk, + reset, tx_lclk, tx_lclk90, tx_lclk_div4, s_axi_aclk, m_axi_aclk, ecfg_tx_enable, ecfg_tx_gpio_enable, ecfg_tx_mmu_enable, ecfg_dataout, emrq_access, emrq_write, emrq_datamode, emrq_ctrlmode, emrq_dstaddr, emrq_data, emrq_srcaddr, emwr_access, @@ -21,8 +21,8 @@ module etx(/*AUTOARG*/ //Clocks and reset input reset; input tx_lclk; //high speed serdes clock - input tx_lclk_out; //lclk output - input tx_lclk_par; //slow speed parallel clock + input tx_lclk90; //lclk output + input tx_lclk_div4; //slow speed parallel clock input s_axi_aclk; //clock for read request and write fifos input m_axi_aclk; //clock for read response fifo @@ -148,7 +148,7 @@ module etx(/*AUTOARG*/ .fifo_full (em@"(substring vl-cell-name 2 4)"_fifo_full), .fifo_progfull (em@"(substring vl-cell-name 2 4)"_progfull), // Inputs - .rd_clk (tx_lclk_par), + .rd_clk (tx_lclk_div4), .wr_clk (@"(substring vl-cell-name 0 1)"_axi_aclk), .reset (reset), .fifo_read (em@"(substring vl-cell-name 2 4)"_rd_en), @@ -171,7 +171,7 @@ module etx(/*AUTOARG*/ .emesh_srcaddr_out(emwr_fifo_srcaddr[31:0]), // Templated .fifo_progfull (emwr_progfull), // Templated // Inputs - .rd_clk (tx_lclk_par), // Templated + .rd_clk (tx_lclk_div4), // Templated .wr_clk (s_axi_aclk), // Templated .reset (reset), // Templated .emesh_access_in (emwr_access), // Templated @@ -196,7 +196,7 @@ module etx(/*AUTOARG*/ .emesh_srcaddr_out(emrq_fifo_srcaddr[31:0]), // Templated .fifo_progfull (emrq_progfull), // Templated // Inputs - .rd_clk (tx_lclk_par), // Templated + .rd_clk (tx_lclk_div4), // Templated .wr_clk (s_axi_aclk), // Templated .reset (reset), // Templated .emesh_access_in (emrq_access), // Templated @@ -223,7 +223,7 @@ module etx(/*AUTOARG*/ .emesh_srcaddr_out(emrr_fifo_srcaddr[31:0]), // Templated .fifo_progfull (emrr_progfull), // Templated // Inputs - .rd_clk (tx_lclk_par), // Templated + .rd_clk (tx_lclk_div4), // Templated .wr_clk (m_axi_aclk), // Templated .reset (reset), // Templated .emesh_access_in (emrr_access), // Templated @@ -256,7 +256,7 @@ module etx(/*AUTOARG*/ .etx_srcaddr (etx_srcaddr[31:0]), .etx_data (etx_data[31:0]), // Inputs - .tx_lclk_par (tx_lclk_par), + .tx_lclk_div4 (tx_lclk_div4), .reset (reset), .emwr_fifo_access (emwr_fifo_access), .emwr_fifo_write (emwr_fifo_write), @@ -306,7 +306,7 @@ module etx(/*AUTOARG*/ .etx_dstaddr (etx_dstaddr[31:0]), .etx_srcaddr (etx_srcaddr[31:0]), .etx_data (etx_data[31:0]), - .tx_lclk_par (tx_lclk_par), + .tx_lclk_div4 (tx_lclk_div4), .tx_rd_wait (tx_rd_wait), .tx_wr_wait (tx_wr_wait)); @@ -334,9 +334,9 @@ module etx(/*AUTOARG*/ .txi_wr_wait_n (txi_wr_wait_n), .txi_rd_wait_p (txi_rd_wait_p), .txi_rd_wait_n (txi_rd_wait_n), - .tx_lclk_par (tx_lclk_par), + .tx_lclk_div4 (tx_lclk_div4), .tx_lclk (tx_lclk), - .tx_lclk_out (tx_lclk_out), + .tx_lclk90 (tx_lclk90), .tx_frame_par (tx_frame_par[7:0]), .tx_data_par (tx_data_par[63:0]), .ecfg_tx_enable (ecfg_tx_enable), @@ -347,7 +347,7 @@ module etx(/*AUTOARG*/ /************************************************************/ /*Debug signals */ /************************************************************/ - always @ (posedge tx_lclk_par) + always @ (posedge tx_lclk_div4) begin ecfg_tx_debug[15:0] <= {2'b0, //15:14 etx_rd_wait, //13 diff --git a/elink/hdl/etx_arbiter.v b/elink/hdl/etx_arbiter.v index 765d1c5..2001749 100644 --- a/elink/hdl/etx_arbiter.v +++ b/elink/hdl/etx_arbiter.v @@ -19,7 +19,7 @@ module etx_arbiter (/*AUTOARG*/ emwr_rd_en, emrq_rd_en, emrr_rd_en, etx_access, etx_write, etx_datamode, etx_ctrlmode, etx_dstaddr, etx_srcaddr, etx_data, // Inputs - tx_lclk_par, reset, emwr_fifo_access, emwr_fifo_write, + tx_lclk_div4, reset, emwr_fifo_access, emwr_fifo_write, emwr_fifo_datamode, emwr_fifo_ctrlmode, emwr_fifo_dstaddr, emwr_fifo_data, emwr_fifo_srcaddr, emrq_fifo_access, emrq_fifo_write, emrq_fifo_datamode, emrq_fifo_ctrlmode, @@ -30,7 +30,7 @@ module etx_arbiter (/*AUTOARG*/ ); // tx clock - input tx_lclk_par; + input tx_lclk_div4; input reset; //Write Request (from slave) @@ -109,7 +109,7 @@ module etx_arbiter (/*AUTOARG*/ assign emrq_rd_en = rq_ready & (~ready | etx_ack); assign emwr_rd_en = wr_ready & (~ready | etx_ack); - always @ (posedge tx_lclk_par) + always @ (posedge tx_lclk_div4) if( reset ) begin ready <= 1'b0; diff --git a/elink/hdl/etx_io.v b/elink/hdl/etx_io.v index 35a5d67..16846d2 100644 --- a/elink/hdl/etx_io.v +++ b/elink/hdl/etx_io.v @@ -4,7 +4,7 @@ module etx_io (/*AUTOARG*/ txo_data_n, tx_wr_wait, tx_rd_wait, // Inputs reset, txi_wr_wait_p, txi_wr_wait_n, txi_rd_wait_p, txi_rd_wait_n, - tx_lclk_par, tx_lclk, tx_lclk_out, tx_frame_par, tx_data_par, + tx_lclk_div4, tx_lclk, tx_lclk90, tx_frame_par, tx_data_par, ecfg_tx_enable, ecfg_tx_gpio_enable, ecfg_dataout ); @@ -26,9 +26,9 @@ module etx_io (/*AUTOARG*/ //############# //# Fabric interface //############# - input tx_lclk_par; // Slow lclk for parallel side (bit rate / 8) - input tx_lclk; // High speed clock for serdesd (bit rate / 2) - input tx_lclk_out; // High speed lclk output clock (90deg from tx_lclk) + input tx_lclk_div4; // Slow lclk for parallel side (bit rate / 8) + input tx_lclk; // High speed clock for serdesd (bit rate / 2) + input tx_lclk90; // High speed lclk output clock (90deg from tx_lclk) input [7:0] tx_frame_par; // Parallel frame for serdes input [63:0] tx_data_par; // Parallel data for serdes @@ -68,7 +68,7 @@ module etx_io (/*AUTOARG*/ assign txgpio = txgpio_sync[0]; // Sync these control bits into our domain - always @ (posedge tx_lclk_par) + always @ (posedge tx_lclk_div4) begin txenb_sync[1:0] <= {ecfg_tx_enable, txenb_sync[1]}; txgpio_sync[1:0] <= {ecfg_tx_gpio_enable, txgpio_sync[1]}; @@ -117,7 +117,7 @@ module etx_io (/*AUTOARG*/ .TFB(), // 1-bit output: 3-state control .TQ(tx_data_t[i]), // 1-bit output: 3-state control .CLK(tx_lclk), // 1-bit input: High speed clock - .CLKDIV(tx_lclk_par), // 1-bit input: Divided clock + .CLKDIV(tx_lclk_div4), // 1-bit input: Divided clock // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each) .D1(pdata[i+56]), // First data out .D2(pdata[i+48]), @@ -166,7 +166,7 @@ module etx_io (/*AUTOARG*/ .TFB(), // 1-bit output: 3-state control .TQ(), // 1-bit output: 3-state control .CLK(tx_lclk), // 1-bit input: High speed clock - .CLKDIV(tx_lclk_par), // 1-bit input: Divided clock + .CLKDIV(tx_lclk_div4), // 1-bit input: Divided clock // D1 - D8: 1-bit (each) input: Parallel data inputs (1-bit each) .D1(pframe[7]), // first data out .D2(pframe[6]), @@ -205,7 +205,7 @@ module etx_io (/*AUTOARG*/ oddr_lclk_inst ( .Q (tx_lclk_buf), - .C (tx_lclk_out), + .C (tx_lclk90), .CE (1'b0), .D1 (ecfg_tx_enable), .D2 (1'b0), diff --git a/elink/hdl/etx_protocol.v b/elink/hdl/etx_protocol.v index c9926f7..67ab127 100644 --- a/elink/hdl/etx_protocol.v +++ b/elink/hdl/etx_protocol.v @@ -14,7 +14,7 @@ module etx_protocol (/*AUTOARG*/ ecfg_tx_datain, // Inputs reset, etx_access, etx_write, etx_datamode, etx_ctrlmode, - etx_dstaddr, etx_srcaddr, etx_data, tx_lclk_par, tx_rd_wait, + etx_dstaddr, etx_srcaddr, etx_data, tx_lclk_div4, tx_rd_wait, tx_wr_wait ); @@ -34,7 +34,7 @@ module etx_protocol (/*AUTOARG*/ output etx_ack; // Parallel interface, 8 eLink bytes at a time - input tx_lclk_par; // Parallel-rate clock from eClock block + input tx_lclk_div4; // Parallel-rate clock from eClock block output [7:0] tx_frame_par; output [63:0] tx_data_par; input tx_rd_wait; // The wait signals are passed through @@ -56,7 +56,7 @@ module etx_protocol (/*AUTOARG*/ // TODO: Bursts - always @( posedge tx_lclk_par or posedge reset ) + always @( posedge tx_lclk_div4 or posedge reset ) begin if(reset) begin @@ -103,7 +103,7 @@ module etx_protocol (/*AUTOARG*/ reg etx_rd_wait; reg etx_wr_wait; - always @ (posedge tx_lclk_par) + always @ (posedge tx_lclk_div4) begin rd_wait_sync <= tx_rd_wait; etx_rd_wait <= rd_wait_sync;