diff --git a/common/dv/dut.v b/common/dv/dut.v index 690f73c..c0ecdbb 100644 --- a/common/dv/dut.v +++ b/common/dv/dut.v @@ -1,9 +1,9 @@ // Standardized "DUT" module dut (/*AUTOARG*/ // Outputs - dut_active, access_out, packet_out, wait_out, + dut_active, clkout, access_out, packet_out, wait_out, // Inputs - clk, nreset, vdd, vss, access_in, packet_in, wait_in + clk1, clk2, nreset, vdd, vss, access_in, packet_in, wait_in ); parameter PW = 99; @@ -12,12 +12,14 @@ module dut (/*AUTOARG*/ //####################################### //# CLOCK AND RESET //####################################### - input clk; + input clk1; + input clk2; input nreset; input [N*N-1:0] vdd; input vss; - output dut_active; //dut ready to go after reset - + output dut_active; // dut ready to go after reset + output clkout; // needed for monitor "source synchronous" + //####################################### //#EMESH INTERFACE //####################################### diff --git a/common/dv/dut_oh_clockdiv.v b/common/dv/dut_oh_clockdiv.v deleted file mode 100644 index 3b03b87..0000000 --- a/common/dv/dut_oh_clockdiv.v +++ /dev/null @@ -1,50 +0,0 @@ -module dut(/*AUTOARG*/ - // Outputs - dut_active, wait_out, access_out, packet_out, - // Inputs - clk, nreset, vdd, vss, access_in, packet_in, wait_in - ); - - parameter N = 1; - parameter PW = 104; - - //clock, reset - input clk; - input nreset; - input [N*N-1:0] vdd; - input vss; - output dut_active; - - //Stimulus Driven Transaction - input [N-1:0] access_in; - input [N*PW-1:0] packet_in; - output [N-1:0] wait_out; - - //DUT driven transactoin - output [N-1:0] access_out; - output [N*PW-1:0] packet_out; - input [N-1:0] wait_in; - - /*AUTOINPUT*/ - /*AUTOOUTPUT*/ - /*AUTOWIRE*/ - - - //tie offs for Dv - assign dut_active = 1'b1; - assign wait_out = 1'b0; - - oh_clockdiv oh_clockdiv (.clkout (clkout), - .clkout90 (clkout90), - .clk (clk), - .nreset (nreset), - .en (1'b1), - .divcfg (packet_in[11:8]) - ); - - -endmodule // dv_elink -// Local Variables: -// verilog-library-directories:("." "../hdl" "../../emesh/dv" "../../emesh/hdl") -// End: - diff --git a/common/dv/dut_oh_debouncer.v b/common/dv/dut_oh_debouncer.v deleted file mode 100644 index 7ba65ac..0000000 --- a/common/dv/dut_oh_debouncer.v +++ /dev/null @@ -1,49 +0,0 @@ -module dut(/*AUTOARG*/ - // Outputs - dut_active, wait_out, access_out, packet_out, - // Inputs - clk, nreset, vdd, vss, access_in, packet_in, wait_in - ); - - parameter N = 1; - parameter PW = 104; - - //clock, reset - input clk; - input nreset; - input [N*N-1:0] vdd; - input vss; - output dut_active; - - //Stimulus Driven Transaction - input [N-1:0] access_in; - input [N*PW-1:0] packet_in; - output [N-1:0] wait_out; - - //DUT driven transactoin - output [N-1:0] access_out; - output [N*PW-1:0] packet_out; - input [N-1:0] wait_in; - - /*AUTOINPUT*/ - /*AUTOOUTPUT*/ - /*AUTOWIRE*/ - - - //tie offs for Dv - assign dut_active = 1'b1; - assign wait_out = 1'b0; - - - oh_debouncer #(.CLKPERIOD(10)) - oh_debouncer (.clean_out (clean_out), - .nreset (nreset), - .clk (clk), - .noisy_in (packet_in[PW-1]) - ); - -endmodule // dv_elink -// Local Variables: -// verilog-library-directories:("." "../hdl" "../../emesh/dv" "../../emesh/hdl") -// End: - diff --git a/common/dv/dut_oh_gray.v b/common/dv/dut_oh_gray.v deleted file mode 100644 index e3620b3..0000000 --- a/common/dv/dut_oh_gray.v +++ /dev/null @@ -1,56 +0,0 @@ -module dut(/*AUTOARG*/ - // Outputs - dut_active, wait_out, access_out, packet_out, - // Inputs - clk, nreset, vdd, vss, access_in, packet_in, wait_in - ); - - parameter N = 1; - parameter PW = 104; - - //clock, reset - input clk; - input nreset; - input [N*N-1:0] vdd; - input vss; - output dut_active; - - //Stimulus Driven Transaction - input [N-1:0] access_in; - input [N*PW-1:0] packet_in; - output [N-1:0] wait_out; - - //DUT driven transactoin - output [N-1:0] access_out; - output [N*PW-1:0] packet_out; - input [N-1:0] wait_in; - - /*AUTOINPUT*/ - /*AUTOOUTPUT*/ - /*AUTOWIRE*/ - - wire [31:0] gray; - - //tie offs for Dv - assign dut_active = 1'b1; - assign wait_out = 1'b0; - - //convert binary to gray - oh_bin2gray #(.DW(32)) - b2g (.gray (gray[31:0]), - .bin (packet_in[39:8])); - - //convert gray back to binary - oh_gray2bin #(.DW(32)) - g2b(.bin (packet_out[39:8]), - .gray (gray[31:0])); - - //check for error - assign error = |(packet_in[39:8] ^ packet_out[39:8]); - -endmodule // dut - -// Local Variables: -// verilog-library-directories:("." "../hdl" "../../emesh/dv" "../../emesh/hdl") -// End: - diff --git a/common/dv/dv_ctrl.v b/common/dv/dv_ctrl.v index ec255fd..fc075b4 100644 --- a/common/dv/dv_ctrl.v +++ b/common/dv/dv_ctrl.v @@ -1,17 +1,20 @@ /* verilator lint_off STMTDLY */ module dv_ctrl(/*AUTOARG*/ // Outputs - nreset, clk, start, + nreset, clk1, clk2, start, // Inputs dut_active, stim_done, test_done ); - parameter CLK_PERIOD = 10; - parameter CLK_PHASE = CLK_PERIOD/2; - parameter TIMEOUT = 5000; + parameter CFG_CLK1_PERIOD = 10; + parameter CFG_CLK1_PHASE = CFG_CLK1_PERIOD/2; + parameter CFG_CLK2_PERIOD = 100; + parameter CFG_CLK2_PHASE = CFG_CLK2_PERIOD/2; + parameter CFG_TIMEOUT = 5000; output nreset; // async active low reset - output clk; // main clock + output clk1; // main clock + output clk2; // secondary clock output start; // start test (level) input dut_active; // reset sequence is done @@ -19,35 +22,67 @@ module dv_ctrl(/*AUTOARG*/ input test_done; //test is done //signal declarations - reg nreset; - reg start; - reg clk=0; + reg nreset; + reg start; + reg clk1=0; + reg clk2=0; + reg [6:0] clk1_phase; + reg [6:0] clk2_phase; + integer seed,r; + + //################################# + // RANDOM NUMBER GENERATOR + // (SEED SUPPLIED EXERNALLY) + //################################# + initial + begin + r=$value$plusargs("SEED=%s", seed); + $display("SEED=%d", seed); +`ifdef CFG_RANDOM + clk1_phase = {$random(seed)}; //generate random values + clk2_phase = {$random(seed)}; //generate random values +`else + clk1_phase = CFG_CLK1_PHASE; + clk2_phase = CFG_CLK2_PHASE; +`endif + $display("clk1_phase=%d clk2_phase=%d", clk1_phase,clk2_phase); + end + //################################# + //CLK1 GENERATOR + //################################# + always + #(clk1_phase + 1) clk1 = ~clk1; //add one to avoid "DC" state + + //################################# + //CLK2 GENERATOR + //################################# + always + #(clk2_phase + 1) clk2 = ~clk2; + + //################################# //RESET + //################################# initial begin #(1) nreset = 'b0; - #(CLK_PERIOD*20) //hold reset for 20 cycles + #(clk1_phase * 20) //hold reset for 20 clk cycles nreset = 'b1; end //START TEST - always @ (posedge clk or negedge nreset) + always @ (posedge clk1 or negedge nreset) if(!nreset) start = 1'b0; else if(dut_active) start = 1'b1; //STOP SIMULATION - always @ (posedge clk) + always @ (posedge clk1) if(stim_done & test_done) - #(TIMEOUT) $finish; + #(CFG_TIMEOUT) $finish; - //CLOCK GENERATOR - always - #(CLK_PHASE) clk = ~clk; - //WAVEFORM DUMP //Better solution? `ifndef VERILATOR diff --git a/common/dv/dv_driver.v b/common/dv/dv_driver.v index 71b34bc..95551d0 100644 --- a/common/dv/dv_driver.v +++ b/common/dv/dv_driver.v @@ -3,20 +3,22 @@ module dv_driver (/*AUTOARG*/ // Outputs stim_access, stim_packet, stim_wait, stim_done, // Inputs - clk, nreset, start, coreid, dut_access, dut_packet, dut_wait + clkin, clkout, nreset, start, coreid, dut_access, dut_packet, + dut_wait ); //Parameters - parameter N = 1; // "N" packets wide - parameter AW = 32; // address width - parameter IDW = 12; // id width - parameter NAME = "none"; // north, south etc - parameter STIMS = 1; // number of stimulus - parameter MAW = 16; // 64KB memory address width - localparam PW =2*AW+40; // packet width (derived) + parameter N = 1; // "N" packets wide + parameter AW = 32; // address width + parameter IDW = 12; // id width + parameter NAME = "none"; // north, south etc + parameter STIMS = 1; // number of stimulus + parameter MAW = 16; // 64KB memory address width + localparam PW = 2*AW+40; // packet width (derived) //Control signals - input clk; + input clkin; + input clkout; input nreset; input start; //starts test input [IDW-1:0] coreid; //everything has a coreid! @@ -63,7 +65,7 @@ module dv_driver (/*AUTOARG*/ .stim_done (stim_vec_done[i]), .stim_wait (stim_wait[i]), // Inputs - .clk (clk), + .clk (clkin), .nreset (nreset), .start (start), .dut_wait (dut_wait[i]) @@ -82,7 +84,7 @@ module dv_driver (/*AUTOARG*/ endgenerate //########################################### - //MONITORS + //MONITORS (USE CLK2) //########################################### //Increment coreID depending on counter and orientation of side block @@ -105,7 +107,7 @@ module dv_driver (/*AUTOARG*/ .IDW(IDW) ) monitor (//inputs - .clk (clk), + .clk (clkout), .nreset (nreset), .dut_access (dut_access[j]), .dut_packet (dut_packet[(j+1)*PW-1:j*PW]), @@ -131,7 +133,7 @@ module dv_driver (/*AUTOARG*/ .access_out (mem_access_out[j]), .packet_out (mem_packet_out[(j+1)*PW-1:j*PW]), // Inputs - .clk (clk), + .clk (clkout), .nreset (nreset), .coreid (coreid[IDW-1:0]), .access_in (dut_access[j]), diff --git a/common/dv/dv_top.v b/common/dv/dv_top.v index fda4b5a..c3ffa72 100644 --- a/common/dv/dv_top.v +++ b/common/dv/dv_top.v @@ -15,7 +15,9 @@ module dv_top(); /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire clk; // From dv_ctrl of dv_ctrl.v + wire clk1; // From dv_ctrl of dv_ctrl.v + wire clk2; // From dv_ctrl of dv_ctrl.v + wire clkout; // From dut of dut.v wire [N-1:0] dut_access; // From dut of dut.v wire dut_active; // From dut of dut.v wire [N*PW-1:0] dut_packet; // From dut of dut.v @@ -46,7 +48,8 @@ module dv_top(); /*AUTOINST*/ // Outputs .nreset (nreset), - .clk (clk), + .clk1 (clk1), + .clk2 (clk2), .start (start), // Inputs .dut_active (dut_active), @@ -60,7 +63,6 @@ module dv_top(); /*dut AUTO_TEMPLATE( .\(.*\)_out (dut_\1[]), .\(.*\)_in (stim_\1[]), - .clk (clk), ); */ @@ -70,11 +72,13 @@ module dv_top(); dut (/*AUTOINST*/ // Outputs .dut_active (dut_active), + .clkout (clkout), .access_out (dut_access[N-1:0]), // Templated .packet_out (dut_packet[N*PW-1:0]), // Templated .wait_out (dut_wait[N-1:0]), // Templated // Inputs - .clk (clk), // Templated + .clk1 (clk1), + .clk2 (clk2), .nreset (nreset), .vdd (vdd[N*N-1:0]), .vss (vss), @@ -89,8 +93,6 @@ module dv_top(); /*dv_driver AUTO_TEMPLATE( .name (@"(substring vl-cell-name 0 2)"_name[]), .coreid (@"(substring vl-cell-name 0 2)"_coreid[IDW-1:0]), - .clk (clk), - .reset (reset), ); */ @@ -100,6 +102,7 @@ module dv_top(); .IDW(IDW) ) dv_driver (.coreid (dv_coreid[IDW-1:0]), + .clkin (clk1), /*AUTOINST*/ // Outputs .stim_access (stim_access[N-1:0]), @@ -107,7 +110,7 @@ module dv_top(); .stim_wait (stim_wait[N-1:0]), .stim_done (stim_done), // Inputs - .clk (clk), // Templated + .clkout (clkout), .nreset (nreset), .start (start), .dut_access (dut_access[N-1:0]),