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Changing dv_* to oh_* to be consistent

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This commit is contained in:
Andreas.Olofsson 2020-04-22 21:52:37 -04:00
parent d9897a1bec
commit cf47e56436
2 changed files with 48 additions and 4 deletions
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38
common/dv/oh_simchecker.v Normal file
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@ -0,0 +1,38 @@
/******************************************************************************
* Function: Results Checker
* Author: Andreas Olofsson
* Copyright: (c) 2020 Adapteva, Inc. All rights reserved.
* ----------------------------------------------------------------------------
* License: This file contains confidential and proprietary information of
* Adapteva. No part of this file may be reproduced, transmitted,
* transcribed, stored in a retrieval system, or translated into any human or
* computer language, in any form or by any means, electronic, mechanical,
* magnetic, optical, chemical, manual, or otherwise, without prior written
* permission of Adapteva. This software may only be used in accordance with
* the terms and conditions of a signed license agreement with Adateva. All
* other use, reproduction or distribution of this software is
* strictly prohibited.
* ----------------------------------------------------------------------------
*
*****************************************************************************/
module dv_checker
(
//Inputs
input clk,
input nreset,
input [DW-1:0] result, // result to check
input [DW-1:0] reference, // reference result
output fail, //fail indicator
);
reg fail;
always @ (negedge clk or negedge nreset)
if(~nreset)
fail <= 1'b0;
else if(result!==reference)
begin
fail <= 1'b1;
$display("ERROR(%0t): result=%b reference=%b", result, reference);
end
endmodule // dv_checker

14
common/dv/dv_ctrl.v → common/dv/oh_siminit.v
View File

@ -1,5 +1,5 @@
/* verilator lint_off STMTDLY */
module dv_ctrl(/*AUTOARG*/
module oh_siminit(/*AUTOARG*/
// Outputs
nreset, clk1, clk2, start, vdd, vss,
// Inputs
@ -42,7 +42,7 @@ module dv_ctrl(/*AUTOARG*/
begin
r=$value$plusargs("SEED=%s", seed);
r=$value$plusargs("TESTNAME=%s", testname[1023:0]);
$display("SEED=%d", seed);
//$display("SEED=%d", seed);
`ifdef CFG_RANDOM
clk1_phase = 1 + {$random(seed)}; //generate random values
clk2_phase = 1 + {$random(seed)}; //generate random values
@ -50,7 +50,7 @@ module dv_ctrl(/*AUTOARG*/
clk1_phase = CFG_CLK1_PHASE;
clk2_phase = CFG_CLK2_PHASE;
`endif
$display("clk1_phase=%d clk2_phase=%d", clk1_phase,clk2_phase);
//$display("clk1_phase=%d clk2_phase=%d", clk1_phase,clk2_phase);
end
//#################################
@ -88,6 +88,7 @@ module dv_ctrl(/*AUTOARG*/
//#################################
//SYNCHRONOUS STIMULUS
//#################################
//START TEST
always @ (posedge clk1 or negedge nreset)
if(!nreset)
@ -103,7 +104,12 @@ module dv_ctrl(/*AUTOARG*/
//$finish;
end
//#################################
// CONFIG
//#################################
initial
$timeformat(-9, 0, " ns", 20);
//#################################
// TIMEOUT
//#################################