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Added missing burst bit for legacy elink...

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- This is a pain in the ass and should never have been implemented in the first place!
- Burst information is contained in two places, once in the first byte being transmitted and once by the frame staying high
- This was done because there was a second special bursting mode where data is streamed into the same address, so bit[2] becomes a "command bit".
This commit is contained in:
Andreas Olofsson 2015-11-17 09:46:22 -05:00
parent ebc55fa0ab
commit d14cc0f258
1 changed files with 11 additions and 6 deletions
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17
elink/hdl/etx_io.v
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@ -89,15 +89,20 @@ module etx_io (/*AUTOARG*/
);
//Sample on aligned edge
reg tx_burst_reg;
always @ (posedge tx_lclk_io)
if(firstedge)
tx_access_reg <= tx_access & ~tx_wait;
begin
tx_access_reg <= tx_access & ~tx_wait;
tx_burst_reg <= tx_burst; //need early indicator for first cycle
end
//Pushback on wait
always @ (posedge tx_lclk_io)
if(firstedge & ~tx_wait & ~((tx_state[2:0]==`CYCLE3) & ~tx_burst))
if(firstedge & ~tx_wait & ~(~tx_burst_reg & tx_state[2:0]==`CYCLE3))
tx_packet_reg[PW-1:0] <= tx_packet[PW-1:0];
//#########################################
//# Transmit state machine
//#########################################
@ -127,8 +132,8 @@ module etx_io (/*AUTOARG*/
`CYCLE4 : tx_state[2:0] <= `CYCLE5;
`CYCLE5 : tx_state[2:0] <= `CYCLE6;
`CYCLE6 : tx_state[2:0] <= `CYCLE7;
`CYCLE7 : tx_state[2:0] <= tx_burst & ~tx_wait ? `CYCLE4 :
`IDLE;
`CYCLE7 : tx_state[2:0] <= tx_burst_reg & ~tx_wait ? `CYCLE4 :
`IDLE;
endcase // case (tx_state)
//#############################
@ -136,7 +141,7 @@ module etx_io (/*AUTOARG*/
//#############################
always @ (posedge tx_lclk_io)
case(tx_state[2:0])
`CYCLE1 : tx_data16[15:0] <= {~write,7'b0,ctrlmode[3:0],dstaddr[31:28]};
`CYCLE1 : tx_data16[15:0] <= {~write,6'b0,tx_burst,1'b0,ctrlmode[3:0],dstaddr[31:28]};
`CYCLE2 : tx_data16[15:0] <= dstaddr[27:12];
`CYCLE3 : tx_data16[15:0] <= {dstaddr[11:0],datamode[1:0],write,tx_access};
`CYCLE4 : tx_data16[15:0] <= data[31:16];