diff --git a/common/hdl/oh_iddr.v b/common/hdl/oh_iddr.v
index 57abf67..cf0bb8d 100644
--- a/common/hdl/oh_iddr.v
+++ b/common/hdl/oh_iddr.v
@@ -29,26 +29,26 @@ module oh_iddr (/*AUTOARG*/
    //regs("sl"=stable low, "sh"=stable high)
    reg [DW-1:0]     q1_sl;
    reg [DW-1:0]     q2_sh;
-   reg [DW-1:0]     q2_sl;
+   reg [DW-1:0]     q1;
+   reg [DW-1:0]     q2;
    
-   // sample on rising edge
+   // rising edge sample
    always @ (posedge clk)
      if(ce)
-       q1_sl[DW-1:0] <= #0.2  din[DW-1:0];
-   
-   // sampling on falling edge
+       q1_sl[DW-1:0] <= din[DW-1:0];
+
+   // falling edge sample
    always @ (negedge clk)
      if(ce)
-       q2_sh[DW-1:0] <= #0.2  din[DW-1:0];
-              
-   // same phase sampling the negedge
+       q2_sh[DW-1:0] <= din[DW-1:0];
+   
+   // pipeline for alignment
    always @ (posedge clk)
      if(ce)
-       q2_sl[DW-1:0] <= #0.2 q2_sh[DW-1:0];
-
-   // driving vectors
-   assign q1[DW-1:0] = q1_sl[DW-1:0];   
-   assign q2[DW-1:0] = q2_sl[DW-1:0];
+       begin
+	  q1[DW-1:0] <= q1_sl[DW-1:0];
+	  q2[DW-1:0] <= q2_sh[DW-1:0];
+       end
             
 endmodule // oh_iddr