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Fixing sampling bug

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This commit is contained in:
Andreas Olofsson 2016-02-24 14:25:23 -05:00
parent cdef6141b4
commit d246529b4b
1 changed files with 13 additions and 13 deletions
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26
common/hdl/oh_iddr.v
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@ -29,26 +29,26 @@ module oh_iddr (/*AUTOARG*/
//regs("sl"=stable low, "sh"=stable high) //regs("sl"=stable low, "sh"=stable high)
reg [DW-1:0] q1_sl; reg [DW-1:0] q1_sl;
reg [DW-1:0] q2_sh; reg [DW-1:0] q2_sh;
reg [DW-1:0] q2_sl; reg [DW-1:0] q1;
reg [DW-1:0] q2;
// sample on rising edge // rising edge sample
always @ (posedge clk) always @ (posedge clk)
if(ce) if(ce)
q1_sl[DW-1:0] <= #0.2 din[DW-1:0]; q1_sl[DW-1:0] <= din[DW-1:0];
// sampling on falling edge // falling edge sample
always @ (negedge clk) always @ (negedge clk)
if(ce) if(ce)
q2_sh[DW-1:0] <= #0.2 din[DW-1:0]; q2_sh[DW-1:0] <= din[DW-1:0];
// same phase sampling the negedge // pipeline for alignment
always @ (posedge clk) always @ (posedge clk)
if(ce) if(ce)
q2_sl[DW-1:0] <= #0.2 q2_sh[DW-1:0]; begin
q1[DW-1:0] <= q1_sl[DW-1:0];
// driving vectors q2[DW-1:0] <= q2_sh[DW-1:0];
assign q1[DW-1:0] = q1_sl[DW-1:0]; end
assign q2[DW-1:0] = q2_sl[DW-1:0];
endmodule // oh_iddr endmodule // oh_iddr