diff --git a/mio/hdl/mio_dp.v b/mio/hdl/mio_dp.v index 9326076..1a25f6c 100644 --- a/mio/hdl/mio_dp.v +++ b/mio/hdl/mio_dp.v @@ -63,6 +63,9 @@ module mio_dp (/*AUTOARG*/ .PW(PW)) mtx (/*AUTOINST*/ // Outputs + .tx_empty (tx_empty), + .tx_full (tx_full), + .tx_prog_full (tx_prog_full), .wait_out (wait_out), .tx_access (tx_access), .tx_packet (tx_packet[N-1:0]), diff --git a/mio/hdl/mio_regs.v b/mio/hdl/mio_regs.v index 8086c17..96d77c6 100644 --- a/mio/hdl/mio_regs.v +++ b/mio/hdl/mio_regs.v @@ -22,45 +22,45 @@ module mio_regs (/*AUTOARG*/ ((DEF_CLK+8'd1)>>8'd1); // 270 degrees // clk,reset - input clk; - input nreset; + input clk; + input nreset; // packet interface - input access_in; // incoming access - input [PW-1:0] packet_in; // incoming packet - output wait_out; - output access_out; // outgoing read packet - output [PW-1:0] packet_out; // outgoing read packet - input wait_in; + input access_in; // incoming access + input [PW-1:0] packet_in; // incoming packet + output wait_out; + output access_out; // outgoing read packet + output [PW-1:0] packet_out; // outgoing read packet + input wait_in; // config - output tx_en; // enable tx - output rx_en; // enable rx - output ddr_mode; // ddr mode for mio - output emode; // epiphany packet mode - output amode; // mio packet mode - output dmode; // mio packet mode - output [7:0] datasize; // mio datasize - output lsbfirst; // lsb shift first - output [4:0] ctrlmode; // emode ctrlmode - input [3:0] addrincr; // address update in amode - + output tx_en; // enable tx + output rx_en; // enable rx + output ddr_mode; // ddr mode for mio + output emode; // epiphany packet mode + output amode; // mio packet mode + output dmode; // mio packet mode + output [7:0] datasize; // mio datasize + output lsbfirst; // lsb shift first + output [4:0] ctrlmode; // emode ctrlmode + input [3:0] addrincr; // address update in amode + //address - output [AW-1:0] dstaddr; // destination address for RX dmode + output [AW-1:0] dstaddr; // destination address for RX dmode // clock - output [7:0] clkdiv; // mio clk clock setting - output [15:0] clkphase0; // [7:0]=rising,[15:8]=falling - output [15:0] clkphase1; // [7:0]=rising,[15:8]=falling - + output [7:0] clkdiv; // mio clk clock setting + output [15:0] clkphase0; // [7:0]=rising,[15:8]=falling + output [15:0] clkphase1; // [7:0]=rising,[15:8]=falling + // status - input tx_full; - input tx_prog_full; - input tx_empty; - input rx_full; - input rx_prog_full; - input rx_empty; - + input tx_full; //tx fifo is full (should not happen!) + input tx_prog_full; //tx fifo is nearing full + input tx_empty; //tx fifo is empty + input rx_full; //rx fifo is full (should not happen!) + input rx_prog_full; //rx fifo is nearing full + input rx_empty; //rx fifo is empty + //###################################################################### //# BODY //###################################################################### diff --git a/mio/hdl/mtx.v b/mio/hdl/mtx.v index 803a63c..dfb3c7c 100644 --- a/mio/hdl/mtx.v +++ b/mio/hdl/mtx.v @@ -1,7 +1,7 @@ `include "mio_constants.vh" module mtx (/*AUTOARG*/ // Outputs - wait_out, tx_access, tx_packet, + tx_empty, tx_full, tx_prog_full, wait_out, tx_access, tx_packet, // Inputs clk, io_clk, nreset, tx_en, datasize, ddr_mode, lsbfirst, access_in, packet_in, tx_wait @@ -19,24 +19,29 @@ module mtx (/*AUTOARG*/ localparam CW = $clog2(2*PW/N); // transfer count width //reset, clk, cfg - input clk; // main core clock - input io_clk; // clock for tx logic - input nreset; // async active low reset - input tx_en; // transmit enable - input [7:0] datasize; // size of data transmitted/received - input ddr_mode; // configure mio in ddr mode - input lsbfirst; // send bits lsb first + input clk; // main core clock + input io_clk; // clock for tx logic + input nreset; // async active low reset + input tx_en; // transmit enable + input [7:0] datasize; // size of data transmitted/received + input ddr_mode; // configure mio in ddr mode + input lsbfirst; // send bits lsb first + + //status + output tx_empty; // tx fifo is empty + output tx_full; // tx fifo is full (should never happen!) + output tx_prog_full;// tx is getting full (stop sending!) // data to transmit - input access_in; // fifo data valid - input [PW-1:0] packet_in; // fifo packet - output wait_out; // wait pushback for fifo - + input access_in; // fifo data valid + input [PW-1:0] packet_in; // fifo packet + output wait_out; // wait pushback for fifo + //IO interface (90 deg clock supplied outside this block) - output tx_access; // access signal for IO - output [N-1:0] tx_packet; // packet for IO - input tx_wait; // pushback from IO - + output tx_access; // access signal for IO + output [N-1:0] tx_packet; // packet for IO + input tx_wait; // pushback from IO + //##################################################################### //# BODY //##################################################################### @@ -45,15 +50,12 @@ module mtx (/*AUTOARG*/ /*AUTOINPUT*/ /*AUTOWIRE*/ // Beginning of automatic wires (for undeclared instantiated-module outputs) - wire empty; // From fifo of oh_fifo_cdc.v wire fifo_access; // From fifo of oh_fifo_cdc.v wire [PW-1:0] fifo_packet; // From fifo of oh_fifo_cdc.v wire fifo_wait; // From par2ser of oh_par2ser.v - wire full; // From fifo of oh_fifo_cdc.v wire io_access; // From par2ser of oh_par2ser.v wire [2*N-1:0] io_packet; // From par2ser of oh_par2ser.v wire io_wait; // From mtx_io of mtx_io.v - wire prog_full; // From fifo of oh_fifo_cdc.v // End of automatics //######################################## @@ -61,6 +63,10 @@ module mtx (/*AUTOARG*/ //######################################## /*oh_fifo_cdc AUTO_TEMPLATE ( + // outputs + .prog_full (tx_prog_full), + .full (tx_full), + .empty (tx_empty), .wait_out (wait_out), .access_out (fifo_access), .packet_out (fifo_packet[PW-1:0]), @@ -83,9 +89,9 @@ module mtx (/*AUTOARG*/ .wait_out (wait_out), // Templated .access_out (fifo_access), // Templated .packet_out (fifo_packet[PW-1:0]), // Templated - .prog_full (prog_full), - .full (full), - .empty (empty), + .prog_full (tx_prog_full), // Templated + .full (tx_full), // Templated + .empty (tx_empty), // Templated // Inputs .nreset (nreset), // Templated .clk_in (clk), // Templated