mirror of
https://github.com/aolofsson/oh.git
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Reset and clock cleanup
-In the default mode we now have 7 input clocks to basic elink -This is too many, need to simplify, not reasonable! -But with all the knobs on the MMCM, performance will be great... -WIP on bursting...
This commit is contained in:
Andreas Olofsson
parent
77e210e7c2
commit
d2dcc15c52
@ -2,7 +2,7 @@ module elink_example(/*AUTOARG*/
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// Outputs
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rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p, rxo_rd_wait_n,
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txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n, txo_data_p,
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txo_data_n, chipid, resetb, cclk_p, cclk_n,
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txo_data_n, chipid, chip_resetb, cclk_p, cclk_n,
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// Inputs
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reset, sys_clk_p, sys_clk_n, clkin_p, clkin_n, start, rxi_lclk_p,
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rxi_lclk_n, rxi_frame_p, rxi_frame_n, rxi_data_p, rxi_data_n,
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@ -46,7 +46,7 @@ module elink_example(/*AUTOARG*/
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/*EPIPHANY INTERFACE (I/O PINS) */
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/********************************/
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output [11:0] chipid; // From etx of etx.v
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output resetb; //chip reset for Epiphany (active low)
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output chip_resetb; //chip reset for Epiphany (active low)
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output cclk_p, cclk_n; //high speed clock (up to 1GHz) to Epiphany
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/*AUTOINPUT*/
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@ -54,10 +54,12 @@ module elink_example(/*AUTOARG*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire done; // From egen_txwr of egen.v
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wire rx_clk_pll; // From elink of elink.v
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wire elink_en; // From elink of elink.v
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wire elink_reset; // From eclocks of eclocks.v
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wire rx_lclk; // From eclocks of eclocks.v
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wire rx_lclk_div4; // From eclocks of eclocks.v
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wire soft_reset; // From elink of elink.v
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wire rx_lclk_pll; // From elink of elink.v
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wire rx_ref_clk; // From eclocks of eclocks.v
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wire tx_lclk; // From eclocks of eclocks.v
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wire tx_lclk90; // From eclocks of eclocks.v
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wire tx_lclk_div4; // From eclocks of eclocks.v
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@ -114,9 +116,7 @@ module elink_example(/*AUTOARG*/
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//######
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//CLOCKS
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//######
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eclocks eclocks (
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.clkin_elink (rx_clk_pll),
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.clkin_cclk (pll_clk),
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eclocks eclocks (.hard_reset (reset),
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/*AUTOINST*/
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// Outputs
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.tx_lclk (tx_lclk),
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@ -124,10 +124,15 @@ module elink_example(/*AUTOARG*/
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.tx_lclk_div4 (tx_lclk_div4),
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.rx_lclk (rx_lclk),
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.rx_lclk_div4 (rx_lclk_div4),
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.rx_ref_clk (rx_ref_clk),
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.cclk_p (cclk_p),
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.cclk_n (cclk_n),
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.elink_reset (elink_reset),
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.chip_resetb (chip_resetb),
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// Inputs
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.reset (reset));
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.elink_en (elink_en),
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.sys_clk (sys_clk),
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.rx_lclk_pll (rx_lclk_pll));
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//######
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//ELINK
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@ -140,10 +145,9 @@ module elink_example(/*AUTOARG*/
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.mailbox_full (),
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.timeout (),
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.chipid (),
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.ioreset (reset),
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/*AUTOINST*/
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// Outputs
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.rx_clk_pll (rx_clk_pll),
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.rx_lclk_pll (rx_lclk_pll),
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.rxo_wr_wait_p (rxo_wr_wait_p),
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.rxo_wr_wait_n (rxo_wr_wait_n),
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.rxo_rd_wait_p (rxo_rd_wait_p),
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@ -154,7 +158,7 @@ module elink_example(/*AUTOARG*/
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.txo_frame_n (txo_frame_n),
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.txo_data_p (txo_data_p[7:0]),
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.txo_data_n (txo_data_n[7:0]),
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.soft_reset (soft_reset),
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.elink_en (elink_en),
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.rxwr_access (rxwr_access),
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.rxwr_packet (rxwr_packet[PW-1:0]),
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.rxrd_access (rxrd_access),
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@ -166,9 +170,11 @@ module elink_example(/*AUTOARG*/
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.reset (reset),
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.sys_clk (sys_clk),
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.tx_lclk (tx_lclk),
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.tx_lclk90 (tx_lclk90),
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.tx_lclk_div4 (tx_lclk_div4),
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.rx_lclk (rx_lclk),
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.rx_lclk_div4 (rx_lclk_div4),
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.rx_ref_clk (rx_ref_clk),
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.rxi_lclk_p (rxi_lclk_p),
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.rxi_lclk_n (rxi_lclk_n),
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.rxi_frame_p (rxi_frame_p),
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@ -1,13 +1,14 @@
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module erx (/*AUTOARG*/
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// Outputs
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rx_clk_pll, rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p,
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rx_lclk_pll, rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p,
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rxo_rd_wait_n, rxwr_access, rxwr_packet, rxrd_access, rxrd_packet,
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rxrr_access, rxrr_packet, erx_cfg_wait, timeout, mailbox_full,
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mailbox_not_empty,
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// Inputs
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reset, ioreset, sys_clk, rx_lclk, rx_lclk_div4, rxi_lclk_p,
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rxi_lclk_n, rxi_frame_p, rxi_frame_n, rxi_data_p, rxi_data_n,
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rxwr_wait, rxrd_wait, rxrr_wait, erx_cfg_access, erx_cfg_packet
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erx_reset, sys_reset, sys_clk, rx_lclk, rx_lclk_div4, rx_ref_clk,
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rxi_lclk_p, rxi_lclk_n, rxi_frame_p, rxi_frame_n, rxi_data_p,
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rxi_data_n, rxwr_wait, rxrd_wait, rxrr_wait, erx_cfg_access,
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erx_cfg_packet
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);
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parameter AW = 32;
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@ -16,13 +17,16 @@ module erx (/*AUTOARG*/
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parameter RFAW = 6;
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parameter ID = 12'h800;
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//Clocks,reset,config
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input reset; // reset for core logic
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input ioreset; // reset for io
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//Synched resets
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input erx_reset; // reset for core logic
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input sys_reset; // reset for fifos
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//Clocks
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input sys_clk; // system clock for rx fifos
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input rx_lclk; // fast clock for io
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input rx_lclk_div4; // slow clock for rest of logic
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output rx_clk_pll; // clock output for pll
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input rx_ref_clk; // idelay reference clock
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output rx_lclk_pll; // clock output for pll
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//FROM IO Pins
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input rxi_lclk_p, rxi_lclk_n; // rx clock input
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@ -80,10 +84,10 @@ module erx (/*AUTOARG*/
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/***********************************************************/
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/*RECEIVER I/O LOGIC */
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/***********************************************************/
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erx_io erx_io (
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/*AUTOINST*/
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erx_io erx_io (.reset (erx_reset),
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/*AUTOINST*/
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// Outputs
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.rx_clk_pll (rx_clk_pll),
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.rx_lclk_pll (rx_lclk_pll),
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.rxo_wr_wait_p (rxo_wr_wait_p),
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.rxo_wr_wait_n (rxo_wr_wait_n),
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.rxo_rd_wait_p (rxo_rd_wait_p),
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@ -92,9 +96,9 @@ module erx (/*AUTOARG*/
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.rx_burst (rx_burst),
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.rx_packet (rx_packet[PW-1:0]),
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// Inputs
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.reset (reset),
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.rx_lclk (rx_lclk),
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.rx_lclk_div4 (rx_lclk_div4),
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.rx_ref_clk (rx_ref_clk),
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.rxi_lclk_p (rxi_lclk_p),
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.rxi_lclk_n (rxi_lclk_n),
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.rxi_frame_p (rxi_frame_p),
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@ -122,6 +126,7 @@ module erx (/*AUTOARG*/
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defparam erx_core.ID=ID;
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erx_core erx_core ( .clk (rx_lclk_div4),
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.reset (erx_reset),
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/*AUTOINST*/
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// Outputs
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.rx_rd_wait (rx_rd_wait), // Templated
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@ -136,7 +141,6 @@ module erx (/*AUTOARG*/
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.mailbox_full (mailbox_full),
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.mailbox_not_empty(mailbox_not_empty),
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// Inputs
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.reset (reset),
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.rx_packet (rx_packet[PW-1:0]), // Templated
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.rx_access (rx_access), // Templated
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.rx_burst (rx_burst),
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@ -162,7 +166,8 @@ module erx (/*AUTOARG*/
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.rxrr_fifo_wait (rxrr_fifo_wait),
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.rxwr_fifo_wait (rxwr_fifo_wait),
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// Inputs
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.reset (reset),
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.erx_reset (erx_reset),
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.sys_reset (sys_reset),
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.rx_lclk_div4 (rx_lclk_div4),
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.sys_clk (sys_clk),
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.rxwr_wait (rxwr_wait),
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@ -177,7 +182,7 @@ module erx (/*AUTOARG*/
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endmodule // erx
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// Local Variables:
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// verilog-library-directories:("." "../../emmu/hdl" "../../edma/hdl" "../../memory/hdl" "../../emailbox/hdl")
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// verilog-library-directories:(".")
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// End:
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/*
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@ -3,8 +3,8 @@ module erx_fifo (/*AUTOARG*/
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rxwr_access, rxwr_packet, rxrd_access, rxrd_packet, rxrr_access,
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rxrr_packet, rxrd_fifo_wait, rxrr_fifo_wait, rxwr_fifo_wait,
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// Inputs
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reset, rx_lclk_div4, sys_clk, rxwr_wait, rxrd_wait, rxrr_wait,
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rxrd_fifo_access, rxrd_fifo_packet, rxrr_fifo_access,
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erx_reset, sys_reset, rx_lclk_div4, sys_clk, rxwr_wait, rxrd_wait,
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rxrr_wait, rxrd_fifo_access, rxrd_fifo_packet, rxrr_fifo_access,
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rxrr_fifo_packet, rxwr_fifo_access, rxwr_fifo_packet
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);
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@ -15,7 +15,8 @@ module erx_fifo (/*AUTOARG*/
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parameter ID = 12'h800;
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//reset & clocks
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input reset;
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input erx_reset;
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input sys_reset;
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input rx_lclk_div4;
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input sys_clk;
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@ -70,7 +71,8 @@ module erx_fifo (/*AUTOARG*/
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.clk_in (rx_lclk_div4),
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.access_in (@"(substring vl-cell-name 0 4)"_fifo_access),
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.wait_in (@"(substring vl-cell-name 0 4)"_wait),
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.reset (reset),
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.reset_in (erx_reset),
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.reset_out (sys_reset),
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.packet_in (@"(substring vl-cell-name 0 4)"_fifo_packet[PW-1:0]),
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);
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*/
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@ -86,10 +88,11 @@ module erx_fifo (/*AUTOARG*/
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.packet_out (rxrd_packet[PW-1:0]), // Templated
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// Inputs
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.clk_in (rx_lclk_div4), // Templated
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.clk_out (sys_clk), // Templated
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.reset (reset), // Templated
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.reset_in (erx_reset), // Templated
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.access_in (rxrd_fifo_access), // Templated
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.packet_in (rxrd_fifo_packet[PW-1:0]), // Templated
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.clk_out (sys_clk), // Templated
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.reset_out (sys_reset), // Templated
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.wait_in (rxrd_wait)); // Templated
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@ -104,10 +107,11 @@ module erx_fifo (/*AUTOARG*/
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.packet_out (rxwr_packet[PW-1:0]), // Templated
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// Inputs
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.clk_in (rx_lclk_div4), // Templated
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.clk_out (sys_clk), // Templated
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.reset (reset), // Templated
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.reset_in (erx_reset), // Templated
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.access_in (rxwr_fifo_access), // Templated
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.packet_in (rxwr_fifo_packet[PW-1:0]), // Templated
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.clk_out (sys_clk), // Templated
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.reset_out (sys_reset), // Templated
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.wait_in (rxwr_wait)); // Templated
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@ -122,10 +126,11 @@ module erx_fifo (/*AUTOARG*/
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.packet_out (rxrr_packet[PW-1:0]), // Templated
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// Inputs
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.clk_in (rx_lclk_div4), // Templated
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.clk_out (sys_clk), // Templated
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.reset (reset), // Templated
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.reset_in (erx_reset), // Templated
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.access_in (rxrr_fifo_access), // Templated
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.packet_in (rxrr_fifo_packet[PW-1:0]), // Templated
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.clk_out (sys_clk), // Templated
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.reset_out (sys_reset), // Templated
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.wait_in (rxrr_wait)); // Templated
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endmodule // erx
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@ -1,10 +1,11 @@
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module erx_io (/*AUTOARG*/
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// Outputs
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rx_clk_pll, rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p,
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rx_lclk_pll, rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p,
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rxo_rd_wait_n, rx_access, rx_burst, rx_packet,
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// Inputs
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reset, rx_lclk, rx_lclk_div4, rxi_lclk_p, rxi_lclk_n, rxi_frame_p,
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rxi_frame_n, rxi_data_p, rxi_data_n, rx_wr_wait, rx_rd_wait
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reset, rx_lclk, rx_lclk_div4, rx_ref_clk, rxi_lclk_p, rxi_lclk_n,
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rxi_frame_p, rxi_frame_n, rxi_data_p, rxi_data_n, rx_wr_wait,
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rx_rd_wait
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);
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parameter IOSTANDARD = "LVDS_25";
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@ -16,7 +17,8 @@ module erx_io (/*AUTOARG*/
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input reset; // reset
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input rx_lclk; // fast I/O clock
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input rx_lclk_div4; // slow clock
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output rx_clk_pll; // clock output for pll
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input rx_ref_clk; // idelay reference clock
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output rx_lclk_pll; // clock output for pll
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//##########################
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//# elink pins
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@ -89,7 +91,7 @@ module erx_io (/*AUTOARG*/
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ibuf_lclk
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(.I (rxi_lclk_p),
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.IB (rxi_lclk_n),
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.O (rx_clk_pll)
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.O (rx_lclk_pll)
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);
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//#####################
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@ -131,11 +133,11 @@ module erx_io (/*AUTOARG*/
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//write Pointer
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always @ (posedge rx_lclk)
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if (~rx_frame)
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rx_pointer[6:0]<=7'b0000001; //new frame
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rx_pointer[6:0] <= 7'b0000001; //new frame
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else if (rx_pointer[6])
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rx_pointer[6:0]<=7'b0001000; //anticipate burst
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rx_pointer[6:0] <= 7'b0001000; //anticipate burst
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else if(rx_frame)
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rx_pointer[6:0]<={rx_pointer[5:0],1'b0};//middle of frame
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rx_pointer[6:0] <= {rx_pointer[5:0],1'b0};//middle of frame
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//convert to 112 bit packet
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always @ (posedge rx_lclk)
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@ -269,7 +271,7 @@ endmodule // erx_io
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/*
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Andreas Olofsson <fred@adapteva.com>
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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@ -49,7 +49,6 @@ endmodule // erx_protocol
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This file is part of the Parallella Project.
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Fred Huettig <fred@adapteva.com>
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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@ -4,7 +4,7 @@ module etx(/*AUTOARG*/
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txo_data_n, txrd_wait, txwr_wait, txrr_wait, etx_cfg_access,
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etx_cfg_packet,
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// Inputs
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reset, ioreset, sys_clk, tx_lclk, tx_lclk90, tx_lclk_div4,
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etx_reset, sys_reset, sys_clk, tx_lclk, tx_lclk90, tx_lclk_div4,
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txi_wr_wait_p, txi_wr_wait_n, txi_rd_wait_p, txi_rd_wait_n,
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txrd_access, txrd_packet, txwr_access, txwr_packet, txrr_access,
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txrr_packet, etx_cfg_wait
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@ -15,9 +15,11 @@ module etx(/*AUTOARG*/
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parameter RFAW = 6;
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parameter ID = 12'h000;
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//Clocks,reset,config
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input reset; // reset for core logic
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input ioreset; // reset for io
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//Synched resets
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input etx_reset; // reset for core logic
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input sys_reset; // reset for fifos
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//Clocks
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input sys_clk; // clock for fifos
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input tx_lclk; // fast clock for io
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input tx_lclk90; // 90 deg shifted lclk
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@ -89,7 +91,8 @@ module etx(/*AUTOARG*/
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.txwr_fifo_access (txwr_fifo_access),
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.txwr_fifo_packet (txwr_fifo_packet[PW-1:0]),
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// Inputs
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.reset (reset),
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.etx_reset (etx_reset),
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.sys_reset (sys_reset),
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.sys_clk (sys_clk),
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.tx_lclk_div4 (tx_lclk_div4),
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.txrd_access (txrd_access),
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@ -124,6 +127,7 @@ module etx(/*AUTOARG*/
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defparam etx_core.ID=ID;
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etx_core etx_core (.clk (tx_lclk_div4),
|
||||
.reset (etx_reset),
|
||||
/*AUTOINST*/
|
||||
// Outputs
|
||||
.tx_access (tx_access), // Templated
|
||||
@ -135,7 +139,6 @@ module etx(/*AUTOARG*/
|
||||
.etx_cfg_access (etx_cfg_access), // Templated
|
||||
.etx_cfg_packet (etx_cfg_packet[PW-1:0]), // Templated
|
||||
// Inputs
|
||||
.reset (reset),
|
||||
.tx_io_wait (tx_io_wait), // Templated
|
||||
.tx_rd_wait (tx_rd_wait), // Templated
|
||||
.tx_wr_wait (tx_wr_wait), // Templated
|
||||
@ -152,11 +155,11 @@ module etx(/*AUTOARG*/
|
||||
/*TRANSMIT I/O LOGIC */
|
||||
/***********************************************************/
|
||||
|
||||
etx_io etx_io (
|
||||
/*AUTOINST*/
|
||||
etx_io etx_io (.reset (etx_reset),
|
||||
/*AUTOINST*/
|
||||
// Outputs
|
||||
.txo_lclk_p (txo_lclk_p),
|
||||
.txo_lclk_n (txo_lclk_n),
|
||||
.txo_lclk_n (txo_lclk_n),
|
||||
.txo_frame_p (txo_frame_p),
|
||||
.txo_frame_n (txo_frame_n),
|
||||
.txo_data_p (txo_data_p[7:0]),
|
||||
@ -165,7 +168,6 @@ module etx(/*AUTOARG*/
|
||||
.tx_wr_wait (tx_wr_wait),
|
||||
.tx_rd_wait (tx_rd_wait),
|
||||
// Inputs
|
||||
.ioreset (ioreset),
|
||||
.tx_lclk (tx_lclk),
|
||||
.tx_lclk90 (tx_lclk90),
|
||||
.tx_lclk_div4 (tx_lclk_div4),
|
||||
|
||||
@ -4,10 +4,11 @@ module etx_fifo(/*AUTOARG*/
|
||||
txrd_fifo_access, txrd_fifo_packet, txrr_fifo_access,
|
||||
txrr_fifo_packet, txwr_fifo_access, txwr_fifo_packet,
|
||||
// Inputs
|
||||
reset, sys_clk, tx_lclk_div4, txrd_access, txrd_packet,
|
||||
txwr_access, txwr_packet, txrr_access, txrr_packet, etx_cfg_wait,
|
||||
txrd_fifo_wait, txrr_fifo_wait, txwr_fifo_wait
|
||||
etx_reset, sys_reset, sys_clk, tx_lclk_div4, txrd_access,
|
||||
txrd_packet, txwr_access, txwr_packet, txrr_access, txrr_packet,
|
||||
etx_cfg_wait, txrd_fifo_wait, txrr_fifo_wait, txwr_fifo_wait
|
||||
);
|
||||
|
||||
parameter AW = 32;
|
||||
parameter DW = 32;
|
||||
parameter PW = 104;
|
||||
@ -15,7 +16,8 @@ module etx_fifo(/*AUTOARG*/
|
||||
parameter ID = 12'h000;
|
||||
|
||||
//Clocks,reset,config
|
||||
input reset;
|
||||
input etx_reset;
|
||||
input sys_reset;
|
||||
input sys_clk;
|
||||
input tx_lclk_div4; // slow speed parallel clock
|
||||
|
||||
@ -73,7 +75,8 @@ module etx_fifo(/*AUTOARG*/
|
||||
.clk_in (sys_clk),
|
||||
.access_in (@"(substring vl-cell-name 0 4)"_access),
|
||||
.rd_en (@"(substring vl-cell-name 0 4)"_fifo_read),
|
||||
.reset (reset),
|
||||
.reset_in (sys_reset),
|
||||
.reset_out (etx_reset),
|
||||
.packet_in (@"(substring vl-cell-name 0 4)"_packet[PW-1:0]),
|
||||
);
|
||||
*/
|
||||
@ -87,10 +90,11 @@ module etx_fifo(/*AUTOARG*/
|
||||
.packet_out (txwr_fifo_packet[PW-1:0]), // Templated
|
||||
// Inputs
|
||||
.clk_in (sys_clk), // Templated
|
||||
.clk_out (tx_lclk_div4), // Templated
|
||||
.reset (reset), // Templated
|
||||
.reset_in (sys_reset), // Templated
|
||||
.access_in (txwr_access), // Templated
|
||||
.packet_in (txwr_packet[PW-1:0]), // Templated
|
||||
.clk_out (tx_lclk_div4), // Templated
|
||||
.reset_out (etx_reset), // Templated
|
||||
.wait_in (txwr_fifo_wait)); // Templated
|
||||
|
||||
//Read request fifo (from slave)
|
||||
@ -102,10 +106,11 @@ module etx_fifo(/*AUTOARG*/
|
||||
.packet_out (txrd_fifo_packet[PW-1:0]), // Templated
|
||||
// Inputs
|
||||
.clk_in (sys_clk), // Templated
|
||||
.clk_out (tx_lclk_div4), // Templated
|
||||
.reset (reset), // Templated
|
||||
.reset_in (sys_reset), // Templated
|
||||
.access_in (txrd_access), // Templated
|
||||
.packet_in (txrd_packet[PW-1:0]), // Templated
|
||||
.clk_out (tx_lclk_div4), // Templated
|
||||
.reset_out (etx_reset), // Templated
|
||||
.wait_in (txrd_fifo_wait)); // Templated
|
||||
|
||||
|
||||
@ -120,10 +125,11 @@ module etx_fifo(/*AUTOARG*/
|
||||
.packet_out (txrr_fifo_packet[PW-1:0]), // Templated
|
||||
// Inputs
|
||||
.clk_in (sys_clk), // Templated
|
||||
.clk_out (tx_lclk_div4), // Templated
|
||||
.reset (reset), // Templated
|
||||
.reset_in (sys_reset), // Templated
|
||||
.access_in (txrr_access), // Templated
|
||||
.packet_in (txrr_packet[PW-1:0]), // Templated
|
||||
.clk_out (tx_lclk_div4), // Templated
|
||||
.reset_out (etx_reset), // Templated
|
||||
.wait_in (txrr_fifo_wait)); // Templated
|
||||
|
||||
|
||||
|
||||
@ -3,7 +3,7 @@ module etx_io (/*AUTOARG*/
|
||||
txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n, txo_data_p,
|
||||
txo_data_n, tx_io_wait, tx_wr_wait, tx_rd_wait,
|
||||
// Inputs
|
||||
ioreset, tx_lclk, tx_lclk90, tx_lclk_div4, txi_wr_wait_p,
|
||||
reset, tx_lclk, tx_lclk90, tx_lclk_div4, txi_wr_wait_p,
|
||||
txi_wr_wait_n, txi_rd_wait_p, txi_rd_wait_n, tx_packet, tx_access,
|
||||
tx_burst
|
||||
);
|
||||
@ -14,7 +14,7 @@ module etx_io (/*AUTOARG*/
|
||||
//###########
|
||||
//# reset, clocks
|
||||
//##########
|
||||
input ioreset; //reset for io
|
||||
input reset; //reset for io
|
||||
input tx_lclk; // fast clock for io
|
||||
input tx_lclk90; // fast 90deg shifted lclk
|
||||
input tx_lclk_div4; // slow clock for rest of logic
|
||||
@ -84,7 +84,7 @@ module etx_io (/*AUTOARG*/
|
||||
tx_pointer[7:0] <= 8'b00000001; //new transaction
|
||||
else if (tx_pointer[6] & tx_burst)
|
||||
tx_pointer[7:0] <= 8'b00001000; //burst
|
||||
else
|
||||
else
|
||||
tx_pointer[7:0] <= {tx_pointer[6:0],tx_pointer[7]};
|
||||
|
||||
//#############################
|
||||
@ -93,8 +93,8 @@ module etx_io (/*AUTOARG*/
|
||||
//TODO: cleanup
|
||||
assign tx_io_wait = tx_access & ~tx_burst & ~tx_io_wait_reg;
|
||||
|
||||
always @ (posedge tx_lclk_div4 or posedge ioreset)
|
||||
if(ioreset)
|
||||
always @ (posedge tx_lclk_div4 or posedge reset)
|
||||
if(reset)
|
||||
tx_io_wait_reg <= 1'b0;
|
||||
else
|
||||
tx_io_wait_reg <= tx_io_wait;
|
||||
@ -102,8 +102,8 @@ module etx_io (/*AUTOARG*/
|
||||
//#############################
|
||||
//# Frame Signal
|
||||
//#############################
|
||||
always @ (posedge tx_lclk or posedge ioreset)
|
||||
if(ioreset)
|
||||
always @ (posedge tx_lclk or posedge reset)
|
||||
if(reset)
|
||||
tx_frame <= 1'b0;
|
||||
else if(tx_pointer[0] & tx_access)
|
||||
tx_frame <= 1'b1;
|
||||
@ -115,22 +115,22 @@ module etx_io (/*AUTOARG*/
|
||||
//#############################
|
||||
//optimize later...
|
||||
always @ (negedge tx_lclk)
|
||||
case(tx_pointer[6:0])
|
||||
case({tx_access,tx_pointer[6:0]})
|
||||
//Cycle0
|
||||
7'b0000001: tx_data16[15:0] <= {ctrlmode[3:0],dstaddr[31:28],~write,7'b0};
|
||||
8'b10000001: tx_data16[15:0] <= {ctrlmode[3:0],dstaddr[31:28],~write,7'b0};
|
||||
//Cycle1
|
||||
7'b0000010: tx_data16[15:0] <= {dstaddr[19:12],dstaddr[27:20]};
|
||||
8'b10000010: tx_data16[15:0] <= {dstaddr[19:12],dstaddr[27:20]};
|
||||
//Cycle2
|
||||
7'b0000100: tx_data16[15:0] <= {dstaddr[3:0],datamode[1:0],write,access,
|
||||
8'b10000100: tx_data16[15:0] <= {dstaddr[3:0],datamode[1:0],write,access,
|
||||
dstaddr[11:4]};
|
||||
//Cycle3
|
||||
7'b0001000: tx_data16[15:0] <= {data[23:16],data[31:24]};
|
||||
8'b10001000: tx_data16[15:0] <= {data[23:16],data[31:24]};
|
||||
//Cycle4
|
||||
7'b0010000: tx_data16[15:0] <= {data[7:0],data[15:8]};
|
||||
8'b10010000: tx_data16[15:0] <= {data[7:0],data[15:8]};
|
||||
//Cycle5
|
||||
7'b0100000: tx_data16[15:0] <= {srcaddr[23:16],srcaddr[31:24]};
|
||||
8'b10100000: tx_data16[15:0] <= {srcaddr[23:16],srcaddr[31:24]};
|
||||
//Cycle6
|
||||
7'b1000000: tx_data16[15:0] <= {srcaddr[7:0],srcaddr[15:8]};
|
||||
8'b11000000: tx_data16[15:0] <= {srcaddr[7:0],srcaddr[15:8]};
|
||||
default tx_data16[15:0] <= 16'b0;
|
||||
endcase // case (tx_pointer[7:0])
|
||||
|
||||
|
||||
@ -41,35 +41,32 @@ module etx_protocol (/*AUTOARG*/
|
||||
//###################################################################
|
||||
reg tx_access;
|
||||
reg [PW-1:0] tx_packet;
|
||||
reg tx_burst;
|
||||
|
||||
wire tx_rd_wait_sync;
|
||||
wire tx_wr_wait_sync;
|
||||
|
||||
wire etx_write;
|
||||
wire [1:0] etx_datamode;
|
||||
wire [3:0] etx_ctrlmode;
|
||||
wire [AW-1:0] etx_dstaddr;
|
||||
wire [DW-1:0] etx_data;
|
||||
wire [AW-1:0] etx_srcaddr;
|
||||
wire last_write;
|
||||
wire [1:0] last_datamode;
|
||||
wire [3:0] last_ctrlmode;
|
||||
wire [AW-1:0] last_dstaddr;
|
||||
wire etx_valid;
|
||||
reg etx_io_wait;
|
||||
|
||||
|
||||
|
||||
wire burst_match;
|
||||
wire burst_type_match;
|
||||
wire [31:0] burst_addr;
|
||||
|
||||
//packet to emesh bundle
|
||||
packet2emesh p2m (
|
||||
// Outputs
|
||||
.access_out (),
|
||||
.write_out (etx_write),
|
||||
.datamode_out (etx_datamode[1:0]),
|
||||
.ctrlmode_out (etx_ctrlmode[3:0]),
|
||||
.dstaddr_out (etx_dstaddr[31:0]),
|
||||
.data_out (etx_data[31:0]),
|
||||
.srcaddr_out (etx_srcaddr[31:0]),
|
||||
// Inputs
|
||||
.packet_in (etx_packet[PW-1:0])
|
||||
);
|
||||
packet2emesh p2m0 (.access_out (),
|
||||
.write_out (etx_write),
|
||||
.datamode_out (etx_datamode[1:0]),
|
||||
.ctrlmode_out (etx_ctrlmode[3:0]),
|
||||
.dstaddr_out (etx_dstaddr[31:0]),
|
||||
.data_out (),
|
||||
.srcaddr_out (),
|
||||
.packet_in (etx_packet[PW-1:0]));//input
|
||||
|
||||
//Only set valid if not wait
|
||||
assign etx_valid = (tx_enable & etx_access & ~(etx_dstaddr[31:20]==ID)) &
|
||||
@ -77,23 +74,43 @@ module etx_protocol (/*AUTOARG*/
|
||||
(~etx_write & ~tx_rd_wait_sync)
|
||||
);
|
||||
|
||||
|
||||
//Prepare transaction / with burst
|
||||
always @ (posedge clk or posedge reset)
|
||||
if(reset)
|
||||
begin
|
||||
tx_packet[PW-1:0] <= 'b0;
|
||||
tx_access <= 1'b0;
|
||||
tx_burst <= 1'b0;//TODO
|
||||
end
|
||||
else if(~tx_io_wait)
|
||||
begin
|
||||
tx_packet[PW-1:0] <= etx_packet[PW-1:0];
|
||||
tx_access <= etx_valid;
|
||||
tx_burst <= 1'b0;//TODO
|
||||
end
|
||||
|
||||
|
||||
//#############################
|
||||
//# Burst Detection
|
||||
//#############################
|
||||
|
||||
packet2emesh p2m1 (.access_out (last_access),
|
||||
.write_out (last_write),
|
||||
.datamode_out (last_datamode[1:0]),
|
||||
.ctrlmode_out (last_ctrlmode[3:0]),
|
||||
.dstaddr_out (last_dstaddr[31:0]),
|
||||
.data_out (),
|
||||
.srcaddr_out (),
|
||||
.packet_in (tx_packet[PW-1:0]));//input
|
||||
|
||||
assign burst_addr[31:0] = last_dstaddr[31:0]+ 4'd8;
|
||||
|
||||
assign burst_type_match = {last_ctrlmode[3:0],last_datamode[1:0],last_write}
|
||||
==
|
||||
{etx_ctrlmode[3:0],etx_datamode[1:0], etx_write};
|
||||
|
||||
assign tx_burst = etx_write & //write
|
||||
(etx_datamode[1:0]==2'b11) & //double only
|
||||
burst_type_match & //same types
|
||||
(burst_addr[31:0]==etx_dstaddr[31:0]); //inc by 8
|
||||
|
||||
//#############################
|
||||
//# Wait signals (async)
|
||||
//#############################
|
||||
@ -124,13 +141,8 @@ endmodule // etx_protocol
|
||||
// End:
|
||||
|
||||
/*
|
||||
File: etx_protocol.v
|
||||
|
||||
This file is part of the Parallella Project.
|
||||
|
||||
Copyright (C) 2014 Adapteva, Inc.
|
||||
Contributed by Fred Huettig <fred@adapteva.com>
|
||||
Contributed by Andreas Olofsson <andreas@adapteva.com>
|
||||
Contributed by Andreas Olofsson <andreas@adapteva.com>
|
||||
|
||||
This program is free software: you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user