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Reset and clock cleanup

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-In the default mode we now have 7 input clocks to basic elink
-This is too many, need to simplify, not reasonable!
-But with all the knobs on the MMCM, performance will be great...
-WIP on bursting...
This commit is contained in:
Andreas Olofsson 2015-05-14 22:31:42 -04:00
parent 77e210e7c2
commit d2dcc15c52
9 changed files with 148 additions and 111 deletions
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28
elink/hdl/elink_example.v
View File

@ -2,7 +2,7 @@ module elink_example(/*AUTOARG*/
// Outputs // Outputs
rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p, rxo_rd_wait_n, rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p, rxo_rd_wait_n,
txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n, txo_data_p, txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n, txo_data_p,
txo_data_n, chipid, resetb, cclk_p, cclk_n, txo_data_n, chipid, chip_resetb, cclk_p, cclk_n,
// Inputs // Inputs
reset, sys_clk_p, sys_clk_n, clkin_p, clkin_n, start, rxi_lclk_p, reset, sys_clk_p, sys_clk_n, clkin_p, clkin_n, start, rxi_lclk_p,
rxi_lclk_n, rxi_frame_p, rxi_frame_n, rxi_data_p, rxi_data_n, rxi_lclk_n, rxi_frame_p, rxi_frame_n, rxi_data_p, rxi_data_n,
@ -46,7 +46,7 @@ module elink_example(/*AUTOARG*/
/*EPIPHANY INTERFACE (I/O PINS) */ /*EPIPHANY INTERFACE (I/O PINS) */
/********************************/ /********************************/
output [11:0] chipid; // From etx of etx.v output [11:0] chipid; // From etx of etx.v
output resetb; //chip reset for Epiphany (active low) output chip_resetb; //chip reset for Epiphany (active low)
output cclk_p, cclk_n; //high speed clock (up to 1GHz) to Epiphany output cclk_p, cclk_n; //high speed clock (up to 1GHz) to Epiphany
/*AUTOINPUT*/ /*AUTOINPUT*/
@ -54,10 +54,12 @@ module elink_example(/*AUTOARG*/
/*AUTOWIRE*/ /*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs) // Beginning of automatic wires (for undeclared instantiated-module outputs)
wire done; // From egen_txwr of egen.v wire done; // From egen_txwr of egen.v
wire rx_clk_pll; // From elink of elink.v wire elink_en; // From elink of elink.v
wire elink_reset; // From eclocks of eclocks.v
wire rx_lclk; // From eclocks of eclocks.v wire rx_lclk; // From eclocks of eclocks.v
wire rx_lclk_div4; // From eclocks of eclocks.v wire rx_lclk_div4; // From eclocks of eclocks.v
wire soft_reset; // From elink of elink.v wire rx_lclk_pll; // From elink of elink.v
wire rx_ref_clk; // From eclocks of eclocks.v
wire tx_lclk; // From eclocks of eclocks.v wire tx_lclk; // From eclocks of eclocks.v
wire tx_lclk90; // From eclocks of eclocks.v wire tx_lclk90; // From eclocks of eclocks.v
wire tx_lclk_div4; // From eclocks of eclocks.v wire tx_lclk_div4; // From eclocks of eclocks.v
@ -114,9 +116,7 @@ module elink_example(/*AUTOARG*/
//###### //######
//CLOCKS //CLOCKS
//###### //######
eclocks eclocks ( eclocks eclocks (.hard_reset (reset),
.clkin_elink (rx_clk_pll),
.clkin_cclk (pll_clk),
/*AUTOINST*/ /*AUTOINST*/
// Outputs // Outputs
.tx_lclk (tx_lclk), .tx_lclk (tx_lclk),
@ -124,10 +124,15 @@ module elink_example(/*AUTOARG*/
.tx_lclk_div4 (tx_lclk_div4), .tx_lclk_div4 (tx_lclk_div4),
.rx_lclk (rx_lclk), .rx_lclk (rx_lclk),
.rx_lclk_div4 (rx_lclk_div4), .rx_lclk_div4 (rx_lclk_div4),
.rx_ref_clk (rx_ref_clk),
.cclk_p (cclk_p), .cclk_p (cclk_p),
.cclk_n (cclk_n), .cclk_n (cclk_n),
.elink_reset (elink_reset),
.chip_resetb (chip_resetb),
// Inputs // Inputs
.reset (reset)); .elink_en (elink_en),
.sys_clk (sys_clk),
.rx_lclk_pll (rx_lclk_pll));
//###### //######
//ELINK //ELINK
@ -140,10 +145,9 @@ module elink_example(/*AUTOARG*/
.mailbox_full (), .mailbox_full (),
.timeout (), .timeout (),
.chipid (), .chipid (),
.ioreset (reset),
/*AUTOINST*/ /*AUTOINST*/
// Outputs // Outputs
.rx_clk_pll (rx_clk_pll), .rx_lclk_pll (rx_lclk_pll),
.rxo_wr_wait_p (rxo_wr_wait_p), .rxo_wr_wait_p (rxo_wr_wait_p),
.rxo_wr_wait_n (rxo_wr_wait_n), .rxo_wr_wait_n (rxo_wr_wait_n),
.rxo_rd_wait_p (rxo_rd_wait_p), .rxo_rd_wait_p (rxo_rd_wait_p),
@ -154,7 +158,7 @@ module elink_example(/*AUTOARG*/
.txo_frame_n (txo_frame_n), .txo_frame_n (txo_frame_n),
.txo_data_p (txo_data_p[7:0]), .txo_data_p (txo_data_p[7:0]),
.txo_data_n (txo_data_n[7:0]), .txo_data_n (txo_data_n[7:0]),
.soft_reset (soft_reset), .elink_en (elink_en),
.rxwr_access (rxwr_access), .rxwr_access (rxwr_access),
.rxwr_packet (rxwr_packet[PW-1:0]), .rxwr_packet (rxwr_packet[PW-1:0]),
.rxrd_access (rxrd_access), .rxrd_access (rxrd_access),
@ -166,9 +170,11 @@ module elink_example(/*AUTOARG*/
.reset (reset), .reset (reset),
.sys_clk (sys_clk), .sys_clk (sys_clk),
.tx_lclk (tx_lclk), .tx_lclk (tx_lclk),
.tx_lclk90 (tx_lclk90),
.tx_lclk_div4 (tx_lclk_div4), .tx_lclk_div4 (tx_lclk_div4),
.rx_lclk (rx_lclk), .rx_lclk (rx_lclk),
.rx_lclk_div4 (rx_lclk_div4), .rx_lclk_div4 (rx_lclk_div4),
.rx_ref_clk (rx_ref_clk),
.rxi_lclk_p (rxi_lclk_p), .rxi_lclk_p (rxi_lclk_p),
.rxi_lclk_n (rxi_lclk_n), .rxi_lclk_n (rxi_lclk_n),
.rxi_frame_p (rxi_frame_p), .rxi_frame_p (rxi_frame_p),

35
elink/hdl/erx.v
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@ -1,13 +1,14 @@
module erx (/*AUTOARG*/ module erx (/*AUTOARG*/
// Outputs // Outputs
rx_clk_pll, rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p, rx_lclk_pll, rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p,
rxo_rd_wait_n, rxwr_access, rxwr_packet, rxrd_access, rxrd_packet, rxo_rd_wait_n, rxwr_access, rxwr_packet, rxrd_access, rxrd_packet,
rxrr_access, rxrr_packet, erx_cfg_wait, timeout, mailbox_full, rxrr_access, rxrr_packet, erx_cfg_wait, timeout, mailbox_full,
mailbox_not_empty, mailbox_not_empty,
// Inputs // Inputs
reset, ioreset, sys_clk, rx_lclk, rx_lclk_div4, rxi_lclk_p, erx_reset, sys_reset, sys_clk, rx_lclk, rx_lclk_div4, rx_ref_clk,
rxi_lclk_n, rxi_frame_p, rxi_frame_n, rxi_data_p, rxi_data_n, rxi_lclk_p, rxi_lclk_n, rxi_frame_p, rxi_frame_n, rxi_data_p,
rxwr_wait, rxrd_wait, rxrr_wait, erx_cfg_access, erx_cfg_packet rxi_data_n, rxwr_wait, rxrd_wait, rxrr_wait, erx_cfg_access,
erx_cfg_packet
); );
parameter AW = 32; parameter AW = 32;
@ -16,13 +17,16 @@ module erx (/*AUTOARG*/
parameter RFAW = 6; parameter RFAW = 6;
parameter ID = 12'h800; parameter ID = 12'h800;
//Clocks,reset,config //Synched resets
input reset; // reset for core logic input erx_reset; // reset for core logic
input ioreset; // reset for io input sys_reset; // reset for fifos
//Clocks
input sys_clk; // system clock for rx fifos input sys_clk; // system clock for rx fifos
input rx_lclk; // fast clock for io input rx_lclk; // fast clock for io
input rx_lclk_div4; // slow clock for rest of logic input rx_lclk_div4; // slow clock for rest of logic
output rx_clk_pll; // clock output for pll input rx_ref_clk; // idelay reference clock
output rx_lclk_pll; // clock output for pll
//FROM IO Pins //FROM IO Pins
input rxi_lclk_p, rxi_lclk_n; // rx clock input input rxi_lclk_p, rxi_lclk_n; // rx clock input
@ -80,10 +84,10 @@ module erx (/*AUTOARG*/
/***********************************************************/ /***********************************************************/
/*RECEIVER I/O LOGIC */ /*RECEIVER I/O LOGIC */
/***********************************************************/ /***********************************************************/
erx_io erx_io ( erx_io erx_io (.reset (erx_reset),
/*AUTOINST*/ /*AUTOINST*/
// Outputs // Outputs
.rx_clk_pll (rx_clk_pll), .rx_lclk_pll (rx_lclk_pll),
.rxo_wr_wait_p (rxo_wr_wait_p), .rxo_wr_wait_p (rxo_wr_wait_p),
.rxo_wr_wait_n (rxo_wr_wait_n), .rxo_wr_wait_n (rxo_wr_wait_n),
.rxo_rd_wait_p (rxo_rd_wait_p), .rxo_rd_wait_p (rxo_rd_wait_p),
@ -92,9 +96,9 @@ module erx (/*AUTOARG*/
.rx_burst (rx_burst), .rx_burst (rx_burst),
.rx_packet (rx_packet[PW-1:0]), .rx_packet (rx_packet[PW-1:0]),
// Inputs // Inputs
.reset (reset),
.rx_lclk (rx_lclk), .rx_lclk (rx_lclk),
.rx_lclk_div4 (rx_lclk_div4), .rx_lclk_div4 (rx_lclk_div4),
.rx_ref_clk (rx_ref_clk),
.rxi_lclk_p (rxi_lclk_p), .rxi_lclk_p (rxi_lclk_p),
.rxi_lclk_n (rxi_lclk_n), .rxi_lclk_n (rxi_lclk_n),
.rxi_frame_p (rxi_frame_p), .rxi_frame_p (rxi_frame_p),
@ -122,6 +126,7 @@ module erx (/*AUTOARG*/
defparam erx_core.ID=ID; defparam erx_core.ID=ID;
erx_core erx_core ( .clk (rx_lclk_div4), erx_core erx_core ( .clk (rx_lclk_div4),
.reset (erx_reset),
/*AUTOINST*/ /*AUTOINST*/
// Outputs // Outputs
.rx_rd_wait (rx_rd_wait), // Templated .rx_rd_wait (rx_rd_wait), // Templated
@ -136,7 +141,6 @@ module erx (/*AUTOARG*/
.mailbox_full (mailbox_full), .mailbox_full (mailbox_full),
.mailbox_not_empty(mailbox_not_empty), .mailbox_not_empty(mailbox_not_empty),
// Inputs // Inputs
.reset (reset),
.rx_packet (rx_packet[PW-1:0]), // Templated .rx_packet (rx_packet[PW-1:0]), // Templated
.rx_access (rx_access), // Templated .rx_access (rx_access), // Templated
.rx_burst (rx_burst), .rx_burst (rx_burst),
@ -162,7 +166,8 @@ module erx (/*AUTOARG*/
.rxrr_fifo_wait (rxrr_fifo_wait), .rxrr_fifo_wait (rxrr_fifo_wait),
.rxwr_fifo_wait (rxwr_fifo_wait), .rxwr_fifo_wait (rxwr_fifo_wait),
// Inputs // Inputs
.reset (reset), .erx_reset (erx_reset),
.sys_reset (sys_reset),
.rx_lclk_div4 (rx_lclk_div4), .rx_lclk_div4 (rx_lclk_div4),
.sys_clk (sys_clk), .sys_clk (sys_clk),
.rxwr_wait (rxwr_wait), .rxwr_wait (rxwr_wait),
@ -177,7 +182,7 @@ module erx (/*AUTOARG*/
endmodule // erx endmodule // erx
// Local Variables: // Local Variables:
// verilog-library-directories:("." "../../emmu/hdl" "../../edma/hdl" "../../memory/hdl" "../../emailbox/hdl") // verilog-library-directories:(".")
// End: // End:
/* /*

25
elink/hdl/erx_fifo.v
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@ -3,8 +3,8 @@ module erx_fifo (/*AUTOARG*/
rxwr_access, rxwr_packet, rxrd_access, rxrd_packet, rxrr_access, rxwr_access, rxwr_packet, rxrd_access, rxrd_packet, rxrr_access,
rxrr_packet, rxrd_fifo_wait, rxrr_fifo_wait, rxwr_fifo_wait, rxrr_packet, rxrd_fifo_wait, rxrr_fifo_wait, rxwr_fifo_wait,
// Inputs // Inputs
reset, rx_lclk_div4, sys_clk, rxwr_wait, rxrd_wait, rxrr_wait, erx_reset, sys_reset, rx_lclk_div4, sys_clk, rxwr_wait, rxrd_wait,
rxrd_fifo_access, rxrd_fifo_packet, rxrr_fifo_access, rxrr_wait, rxrd_fifo_access, rxrd_fifo_packet, rxrr_fifo_access,
rxrr_fifo_packet, rxwr_fifo_access, rxwr_fifo_packet rxrr_fifo_packet, rxwr_fifo_access, rxwr_fifo_packet
); );
@ -15,7 +15,8 @@ module erx_fifo (/*AUTOARG*/
parameter ID = 12'h800; parameter ID = 12'h800;
//reset & clocks //reset & clocks
input reset; input erx_reset;
input sys_reset;
input rx_lclk_div4; input rx_lclk_div4;
input sys_clk; input sys_clk;
@ -70,7 +71,8 @@ module erx_fifo (/*AUTOARG*/
.clk_in (rx_lclk_div4), .clk_in (rx_lclk_div4),
.access_in (@"(substring vl-cell-name 0 4)"_fifo_access), .access_in (@"(substring vl-cell-name 0 4)"_fifo_access),
.wait_in (@"(substring vl-cell-name 0 4)"_wait), .wait_in (@"(substring vl-cell-name 0 4)"_wait),
.reset (reset), .reset_in (erx_reset),
.reset_out (sys_reset),
.packet_in (@"(substring vl-cell-name 0 4)"_fifo_packet[PW-1:0]), .packet_in (@"(substring vl-cell-name 0 4)"_fifo_packet[PW-1:0]),
); );
*/ */
@ -86,10 +88,11 @@ module erx_fifo (/*AUTOARG*/
.packet_out (rxrd_packet[PW-1:0]), // Templated .packet_out (rxrd_packet[PW-1:0]), // Templated
// Inputs // Inputs
.clk_in (rx_lclk_div4), // Templated .clk_in (rx_lclk_div4), // Templated
.clk_out (sys_clk), // Templated .reset_in (erx_reset), // Templated
.reset (reset), // Templated
.access_in (rxrd_fifo_access), // Templated .access_in (rxrd_fifo_access), // Templated
.packet_in (rxrd_fifo_packet[PW-1:0]), // Templated .packet_in (rxrd_fifo_packet[PW-1:0]), // Templated
.clk_out (sys_clk), // Templated
.reset_out (sys_reset), // Templated
.wait_in (rxrd_wait)); // Templated .wait_in (rxrd_wait)); // Templated
@ -104,10 +107,11 @@ module erx_fifo (/*AUTOARG*/
.packet_out (rxwr_packet[PW-1:0]), // Templated .packet_out (rxwr_packet[PW-1:0]), // Templated
// Inputs // Inputs
.clk_in (rx_lclk_div4), // Templated .clk_in (rx_lclk_div4), // Templated
.clk_out (sys_clk), // Templated .reset_in (erx_reset), // Templated
.reset (reset), // Templated
.access_in (rxwr_fifo_access), // Templated .access_in (rxwr_fifo_access), // Templated
.packet_in (rxwr_fifo_packet[PW-1:0]), // Templated .packet_in (rxwr_fifo_packet[PW-1:0]), // Templated
.clk_out (sys_clk), // Templated
.reset_out (sys_reset), // Templated
.wait_in (rxwr_wait)); // Templated .wait_in (rxwr_wait)); // Templated
@ -122,10 +126,11 @@ module erx_fifo (/*AUTOARG*/
.packet_out (rxrr_packet[PW-1:0]), // Templated .packet_out (rxrr_packet[PW-1:0]), // Templated
// Inputs // Inputs
.clk_in (rx_lclk_div4), // Templated .clk_in (rx_lclk_div4), // Templated
.clk_out (sys_clk), // Templated .reset_in (erx_reset), // Templated
.reset (reset), // Templated
.access_in (rxrr_fifo_access), // Templated .access_in (rxrr_fifo_access), // Templated
.packet_in (rxrr_fifo_packet[PW-1:0]), // Templated .packet_in (rxrr_fifo_packet[PW-1:0]), // Templated
.clk_out (sys_clk), // Templated
.reset_out (sys_reset), // Templated
.wait_in (rxrr_wait)); // Templated .wait_in (rxrr_wait)); // Templated
endmodule // erx endmodule // erx

20
elink/hdl/erx_io.v
View File

@ -1,10 +1,11 @@
module erx_io (/*AUTOARG*/ module erx_io (/*AUTOARG*/
// Outputs // Outputs
rx_clk_pll, rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p, rx_lclk_pll, rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p,
rxo_rd_wait_n, rx_access, rx_burst, rx_packet, rxo_rd_wait_n, rx_access, rx_burst, rx_packet,
// Inputs // Inputs
reset, rx_lclk, rx_lclk_div4, rxi_lclk_p, rxi_lclk_n, rxi_frame_p, reset, rx_lclk, rx_lclk_div4, rx_ref_clk, rxi_lclk_p, rxi_lclk_n,
rxi_frame_n, rxi_data_p, rxi_data_n, rx_wr_wait, rx_rd_wait rxi_frame_p, rxi_frame_n, rxi_data_p, rxi_data_n, rx_wr_wait,
rx_rd_wait
); );
parameter IOSTANDARD = "LVDS_25"; parameter IOSTANDARD = "LVDS_25";
@ -16,7 +17,8 @@ module erx_io (/*AUTOARG*/
input reset; // reset input reset; // reset
input rx_lclk; // fast I/O clock input rx_lclk; // fast I/O clock
input rx_lclk_div4; // slow clock input rx_lclk_div4; // slow clock
output rx_clk_pll; // clock output for pll input rx_ref_clk; // idelay reference clock
output rx_lclk_pll; // clock output for pll
//########################## //##########################
//# elink pins //# elink pins
@ -89,7 +91,7 @@ module erx_io (/*AUTOARG*/
ibuf_lclk ibuf_lclk
(.I (rxi_lclk_p), (.I (rxi_lclk_p),
.IB (rxi_lclk_n), .IB (rxi_lclk_n),
.O (rx_clk_pll) .O (rx_lclk_pll)
); );
//##################### //#####################
@ -131,11 +133,11 @@ module erx_io (/*AUTOARG*/
//write Pointer //write Pointer
always @ (posedge rx_lclk) always @ (posedge rx_lclk)
if (~rx_frame) if (~rx_frame)
rx_pointer[6:0]<=7'b0000001; //new frame rx_pointer[6:0] <= 7'b0000001; //new frame
else if (rx_pointer[6]) else if (rx_pointer[6])
rx_pointer[6:0]<=7'b0001000; //anticipate burst rx_pointer[6:0] <= 7'b0001000; //anticipate burst
else if(rx_frame) else if(rx_frame)
rx_pointer[6:0]<={rx_pointer[5:0],1'b0};//middle of frame rx_pointer[6:0] <= {rx_pointer[5:0],1'b0};//middle of frame
//convert to 112 bit packet //convert to 112 bit packet
always @ (posedge rx_lclk) always @ (posedge rx_lclk)
@ -269,7 +271,7 @@ endmodule // erx_io
/* /*
Copyright (C) 2014 Adapteva, Inc. Copyright (C) 2014 Adapteva, Inc.
Contributed by Andreas Olofsson <fred@adapteva.com> Contributed by Andreas Olofsson <andreas@adapteva.com>
This program is free software: you can redistribute it and/or modify This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by it under the terms of the GNU General Public License as published by

1
elink/hdl/erx_protocol.v
View File

@ -49,7 +49,6 @@ endmodule // erx_protocol
This file is part of the Parallella Project. This file is part of the Parallella Project.
Copyright (C) 2014 Adapteva, Inc. Copyright (C) 2014 Adapteva, Inc.
Contributed by Fred Huettig <fred@adapteva.com>
Contributed by Andreas Olofsson <andreas@adapteva.com> Contributed by Andreas Olofsson <andreas@adapteva.com>
This program is free software: you can redistribute it and/or modify This program is free software: you can redistribute it and/or modify

22
elink/hdl/etx.v
View File

@ -4,7 +4,7 @@ module etx(/*AUTOARG*/
txo_data_n, txrd_wait, txwr_wait, txrr_wait, etx_cfg_access, txo_data_n, txrd_wait, txwr_wait, txrr_wait, etx_cfg_access,
etx_cfg_packet, etx_cfg_packet,
// Inputs // Inputs
reset, ioreset, sys_clk, tx_lclk, tx_lclk90, tx_lclk_div4, etx_reset, sys_reset, sys_clk, tx_lclk, tx_lclk90, tx_lclk_div4,
txi_wr_wait_p, txi_wr_wait_n, txi_rd_wait_p, txi_rd_wait_n, txi_wr_wait_p, txi_wr_wait_n, txi_rd_wait_p, txi_rd_wait_n,
txrd_access, txrd_packet, txwr_access, txwr_packet, txrr_access, txrd_access, txrd_packet, txwr_access, txwr_packet, txrr_access,
txrr_packet, etx_cfg_wait txrr_packet, etx_cfg_wait
@ -15,9 +15,11 @@ module etx(/*AUTOARG*/
parameter RFAW = 6; parameter RFAW = 6;
parameter ID = 12'h000; parameter ID = 12'h000;
//Clocks,reset,config //Synched resets
input reset; // reset for core logic input etx_reset; // reset for core logic
input ioreset; // reset for io input sys_reset; // reset for fifos
//Clocks
input sys_clk; // clock for fifos input sys_clk; // clock for fifos
input tx_lclk; // fast clock for io input tx_lclk; // fast clock for io
input tx_lclk90; // 90 deg shifted lclk input tx_lclk90; // 90 deg shifted lclk
@ -89,7 +91,8 @@ module etx(/*AUTOARG*/
.txwr_fifo_access (txwr_fifo_access), .txwr_fifo_access (txwr_fifo_access),
.txwr_fifo_packet (txwr_fifo_packet[PW-1:0]), .txwr_fifo_packet (txwr_fifo_packet[PW-1:0]),
// Inputs // Inputs
.reset (reset), .etx_reset (etx_reset),
.sys_reset (sys_reset),
.sys_clk (sys_clk), .sys_clk (sys_clk),
.tx_lclk_div4 (tx_lclk_div4), .tx_lclk_div4 (tx_lclk_div4),
.txrd_access (txrd_access), .txrd_access (txrd_access),
@ -124,6 +127,7 @@ module etx(/*AUTOARG*/
defparam etx_core.ID=ID; defparam etx_core.ID=ID;
etx_core etx_core (.clk (tx_lclk_div4), etx_core etx_core (.clk (tx_lclk_div4),
.reset (etx_reset),
/*AUTOINST*/ /*AUTOINST*/
// Outputs // Outputs
.tx_access (tx_access), // Templated .tx_access (tx_access), // Templated
@ -135,7 +139,6 @@ module etx(/*AUTOARG*/
.etx_cfg_access (etx_cfg_access), // Templated .etx_cfg_access (etx_cfg_access), // Templated
.etx_cfg_packet (etx_cfg_packet[PW-1:0]), // Templated .etx_cfg_packet (etx_cfg_packet[PW-1:0]), // Templated
// Inputs // Inputs
.reset (reset),
.tx_io_wait (tx_io_wait), // Templated .tx_io_wait (tx_io_wait), // Templated
.tx_rd_wait (tx_rd_wait), // Templated .tx_rd_wait (tx_rd_wait), // Templated
.tx_wr_wait (tx_wr_wait), // Templated .tx_wr_wait (tx_wr_wait), // Templated
@ -152,11 +155,11 @@ module etx(/*AUTOARG*/
/*TRANSMIT I/O LOGIC */ /*TRANSMIT I/O LOGIC */
/***********************************************************/ /***********************************************************/
etx_io etx_io ( etx_io etx_io (.reset (etx_reset),
/*AUTOINST*/ /*AUTOINST*/
// Outputs // Outputs
.txo_lclk_p (txo_lclk_p), .txo_lclk_p (txo_lclk_p),
.txo_lclk_n (txo_lclk_n), .txo_lclk_n (txo_lclk_n),
.txo_frame_p (txo_frame_p), .txo_frame_p (txo_frame_p),
.txo_frame_n (txo_frame_n), .txo_frame_n (txo_frame_n),
.txo_data_p (txo_data_p[7:0]), .txo_data_p (txo_data_p[7:0]),
@ -165,7 +168,6 @@ module etx(/*AUTOARG*/
.tx_wr_wait (tx_wr_wait), .tx_wr_wait (tx_wr_wait),
.tx_rd_wait (tx_rd_wait), .tx_rd_wait (tx_rd_wait),
// Inputs // Inputs
.ioreset (ioreset),
.tx_lclk (tx_lclk), .tx_lclk (tx_lclk),
.tx_lclk90 (tx_lclk90), .tx_lclk90 (tx_lclk90),
.tx_lclk_div4 (tx_lclk_div4), .tx_lclk_div4 (tx_lclk_div4),

28
elink/hdl/etx_fifo.v
View File

@ -4,10 +4,11 @@ module etx_fifo(/*AUTOARG*/
txrd_fifo_access, txrd_fifo_packet, txrr_fifo_access, txrd_fifo_access, txrd_fifo_packet, txrr_fifo_access,
txrr_fifo_packet, txwr_fifo_access, txwr_fifo_packet, txrr_fifo_packet, txwr_fifo_access, txwr_fifo_packet,
// Inputs // Inputs
reset, sys_clk, tx_lclk_div4, txrd_access, txrd_packet, etx_reset, sys_reset, sys_clk, tx_lclk_div4, txrd_access,
txwr_access, txwr_packet, txrr_access, txrr_packet, etx_cfg_wait, txrd_packet, txwr_access, txwr_packet, txrr_access, txrr_packet,
txrd_fifo_wait, txrr_fifo_wait, txwr_fifo_wait etx_cfg_wait, txrd_fifo_wait, txrr_fifo_wait, txwr_fifo_wait
); );
parameter AW = 32; parameter AW = 32;
parameter DW = 32; parameter DW = 32;
parameter PW = 104; parameter PW = 104;
@ -15,7 +16,8 @@ module etx_fifo(/*AUTOARG*/
parameter ID = 12'h000; parameter ID = 12'h000;
//Clocks,reset,config //Clocks,reset,config
input reset; input etx_reset;
input sys_reset;
input sys_clk; input sys_clk;
input tx_lclk_div4; // slow speed parallel clock input tx_lclk_div4; // slow speed parallel clock
@ -73,7 +75,8 @@ module etx_fifo(/*AUTOARG*/
.clk_in (sys_clk), .clk_in (sys_clk),
.access_in (@"(substring vl-cell-name 0 4)"_access), .access_in (@"(substring vl-cell-name 0 4)"_access),
.rd_en (@"(substring vl-cell-name 0 4)"_fifo_read), .rd_en (@"(substring vl-cell-name 0 4)"_fifo_read),
.reset (reset), .reset_in (sys_reset),
.reset_out (etx_reset),
.packet_in (@"(substring vl-cell-name 0 4)"_packet[PW-1:0]), .packet_in (@"(substring vl-cell-name 0 4)"_packet[PW-1:0]),
); );
*/ */
@ -87,10 +90,11 @@ module etx_fifo(/*AUTOARG*/
.packet_out (txwr_fifo_packet[PW-1:0]), // Templated .packet_out (txwr_fifo_packet[PW-1:0]), // Templated
// Inputs // Inputs
.clk_in (sys_clk), // Templated .clk_in (sys_clk), // Templated
.clk_out (tx_lclk_div4), // Templated .reset_in (sys_reset), // Templated
.reset (reset), // Templated
.access_in (txwr_access), // Templated .access_in (txwr_access), // Templated
.packet_in (txwr_packet[PW-1:0]), // Templated .packet_in (txwr_packet[PW-1:0]), // Templated
.clk_out (tx_lclk_div4), // Templated
.reset_out (etx_reset), // Templated
.wait_in (txwr_fifo_wait)); // Templated .wait_in (txwr_fifo_wait)); // Templated
//Read request fifo (from slave) //Read request fifo (from slave)
@ -102,10 +106,11 @@ module etx_fifo(/*AUTOARG*/
.packet_out (txrd_fifo_packet[PW-1:0]), // Templated .packet_out (txrd_fifo_packet[PW-1:0]), // Templated
// Inputs // Inputs
.clk_in (sys_clk), // Templated .clk_in (sys_clk), // Templated
.clk_out (tx_lclk_div4), // Templated .reset_in (sys_reset), // Templated
.reset (reset), // Templated
.access_in (txrd_access), // Templated .access_in (txrd_access), // Templated
.packet_in (txrd_packet[PW-1:0]), // Templated .packet_in (txrd_packet[PW-1:0]), // Templated
.clk_out (tx_lclk_div4), // Templated
.reset_out (etx_reset), // Templated
.wait_in (txrd_fifo_wait)); // Templated .wait_in (txrd_fifo_wait)); // Templated
@ -120,10 +125,11 @@ module etx_fifo(/*AUTOARG*/
.packet_out (txrr_fifo_packet[PW-1:0]), // Templated .packet_out (txrr_fifo_packet[PW-1:0]), // Templated
// Inputs // Inputs
.clk_in (sys_clk), // Templated .clk_in (sys_clk), // Templated
.clk_out (tx_lclk_div4), // Templated .reset_in (sys_reset), // Templated
.reset (reset), // Templated
.access_in (txrr_access), // Templated .access_in (txrr_access), // Templated
.packet_in (txrr_packet[PW-1:0]), // Templated .packet_in (txrr_packet[PW-1:0]), // Templated
.clk_out (tx_lclk_div4), // Templated
.reset_out (etx_reset), // Templated
.wait_in (txrr_fifo_wait)); // Templated .wait_in (txrr_fifo_wait)); // Templated

30
elink/hdl/etx_io.v
View File

@ -3,7 +3,7 @@ module etx_io (/*AUTOARG*/
txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n, txo_data_p, txo_lclk_p, txo_lclk_n, txo_frame_p, txo_frame_n, txo_data_p,
txo_data_n, tx_io_wait, tx_wr_wait, tx_rd_wait, txo_data_n, tx_io_wait, tx_wr_wait, tx_rd_wait,
// Inputs // Inputs
ioreset, tx_lclk, tx_lclk90, tx_lclk_div4, txi_wr_wait_p, reset, tx_lclk, tx_lclk90, tx_lclk_div4, txi_wr_wait_p,
txi_wr_wait_n, txi_rd_wait_p, txi_rd_wait_n, tx_packet, tx_access, txi_wr_wait_n, txi_rd_wait_p, txi_rd_wait_n, tx_packet, tx_access,
tx_burst tx_burst
); );
@ -14,7 +14,7 @@ module etx_io (/*AUTOARG*/
//########### //###########
//# reset, clocks //# reset, clocks
//########## //##########
input ioreset; //reset for io input reset; //reset for io
input tx_lclk; // fast clock for io input tx_lclk; // fast clock for io
input tx_lclk90; // fast 90deg shifted lclk input tx_lclk90; // fast 90deg shifted lclk
input tx_lclk_div4; // slow clock for rest of logic input tx_lclk_div4; // slow clock for rest of logic
@ -84,7 +84,7 @@ module etx_io (/*AUTOARG*/
tx_pointer[7:0] <= 8'b00000001; //new transaction tx_pointer[7:0] <= 8'b00000001; //new transaction
else if (tx_pointer[6] & tx_burst) else if (tx_pointer[6] & tx_burst)
tx_pointer[7:0] <= 8'b00001000; //burst tx_pointer[7:0] <= 8'b00001000; //burst
else else
tx_pointer[7:0] <= {tx_pointer[6:0],tx_pointer[7]}; tx_pointer[7:0] <= {tx_pointer[6:0],tx_pointer[7]};
//############################# //#############################
@ -93,8 +93,8 @@ module etx_io (/*AUTOARG*/
//TODO: cleanup //TODO: cleanup
assign tx_io_wait = tx_access & ~tx_burst & ~tx_io_wait_reg; assign tx_io_wait = tx_access & ~tx_burst & ~tx_io_wait_reg;
always @ (posedge tx_lclk_div4 or posedge ioreset) always @ (posedge tx_lclk_div4 or posedge reset)
if(ioreset) if(reset)
tx_io_wait_reg <= 1'b0; tx_io_wait_reg <= 1'b0;
else else
tx_io_wait_reg <= tx_io_wait; tx_io_wait_reg <= tx_io_wait;
@ -102,8 +102,8 @@ module etx_io (/*AUTOARG*/
//############################# //#############################
//# Frame Signal //# Frame Signal
//############################# //#############################
always @ (posedge tx_lclk or posedge ioreset) always @ (posedge tx_lclk or posedge reset)
if(ioreset) if(reset)
tx_frame <= 1'b0; tx_frame <= 1'b0;
else if(tx_pointer[0] & tx_access) else if(tx_pointer[0] & tx_access)
tx_frame <= 1'b1; tx_frame <= 1'b1;
@ -115,22 +115,22 @@ module etx_io (/*AUTOARG*/
//############################# //#############################
//optimize later... //optimize later...
always @ (negedge tx_lclk) always @ (negedge tx_lclk)
case(tx_pointer[6:0]) case({tx_access,tx_pointer[6:0]})
//Cycle0 //Cycle0
7'b0000001: tx_data16[15:0] <= {ctrlmode[3:0],dstaddr[31:28],~write,7'b0}; 8'b10000001: tx_data16[15:0] <= {ctrlmode[3:0],dstaddr[31:28],~write,7'b0};
//Cycle1 //Cycle1
7'b0000010: tx_data16[15:0] <= {dstaddr[19:12],dstaddr[27:20]}; 8'b10000010: tx_data16[15:0] <= {dstaddr[19:12],dstaddr[27:20]};
//Cycle2 //Cycle2
7'b0000100: tx_data16[15:0] <= {dstaddr[3:0],datamode[1:0],write,access, 8'b10000100: tx_data16[15:0] <= {dstaddr[3:0],datamode[1:0],write,access,
dstaddr[11:4]}; dstaddr[11:4]};
//Cycle3 //Cycle3
7'b0001000: tx_data16[15:0] <= {data[23:16],data[31:24]}; 8'b10001000: tx_data16[15:0] <= {data[23:16],data[31:24]};
//Cycle4 //Cycle4
7'b0010000: tx_data16[15:0] <= {data[7:0],data[15:8]}; 8'b10010000: tx_data16[15:0] <= {data[7:0],data[15:8]};
//Cycle5 //Cycle5
7'b0100000: tx_data16[15:0] <= {srcaddr[23:16],srcaddr[31:24]}; 8'b10100000: tx_data16[15:0] <= {srcaddr[23:16],srcaddr[31:24]};
//Cycle6 //Cycle6
7'b1000000: tx_data16[15:0] <= {srcaddr[7:0],srcaddr[15:8]}; 8'b11000000: tx_data16[15:0] <= {srcaddr[7:0],srcaddr[15:8]};
default tx_data16[15:0] <= 16'b0; default tx_data16[15:0] <= 16'b0;
endcase // case (tx_pointer[7:0]) endcase // case (tx_pointer[7:0])

70
elink/hdl/etx_protocol.v
View File

@ -41,35 +41,32 @@ module etx_protocol (/*AUTOARG*/
//################################################################### //###################################################################
reg tx_access; reg tx_access;
reg [PW-1:0] tx_packet; reg [PW-1:0] tx_packet;
reg tx_burst;
wire tx_rd_wait_sync; wire tx_rd_wait_sync;
wire tx_wr_wait_sync; wire tx_wr_wait_sync;
wire etx_write; wire etx_write;
wire [1:0] etx_datamode; wire [1:0] etx_datamode;
wire [3:0] etx_ctrlmode; wire [3:0] etx_ctrlmode;
wire [AW-1:0] etx_dstaddr; wire [AW-1:0] etx_dstaddr;
wire [DW-1:0] etx_data; wire [DW-1:0] etx_data;
wire [AW-1:0] etx_srcaddr; wire last_write;
wire [1:0] last_datamode;
wire [3:0] last_ctrlmode;
wire [AW-1:0] last_dstaddr;
wire etx_valid; wire etx_valid;
reg etx_io_wait; reg etx_io_wait;
wire burst_match;
wire burst_type_match;
wire [31:0] burst_addr;
//packet to emesh bundle //packet to emesh bundle
packet2emesh p2m ( packet2emesh p2m0 (.access_out (),
// Outputs .write_out (etx_write),
.access_out (), .datamode_out (etx_datamode[1:0]),
.write_out (etx_write), .ctrlmode_out (etx_ctrlmode[3:0]),
.datamode_out (etx_datamode[1:0]), .dstaddr_out (etx_dstaddr[31:0]),
.ctrlmode_out (etx_ctrlmode[3:0]), .data_out (),
.dstaddr_out (etx_dstaddr[31:0]), .srcaddr_out (),
.data_out (etx_data[31:0]), .packet_in (etx_packet[PW-1:0]));//input
.srcaddr_out (etx_srcaddr[31:0]),
// Inputs
.packet_in (etx_packet[PW-1:0])
);
//Only set valid if not wait //Only set valid if not wait
assign etx_valid = (tx_enable & etx_access & ~(etx_dstaddr[31:20]==ID)) & assign etx_valid = (tx_enable & etx_access & ~(etx_dstaddr[31:20]==ID)) &
@ -77,23 +74,43 @@ module etx_protocol (/*AUTOARG*/
(~etx_write & ~tx_rd_wait_sync) (~etx_write & ~tx_rd_wait_sync)
); );
//Prepare transaction / with burst //Prepare transaction / with burst
always @ (posedge clk or posedge reset) always @ (posedge clk or posedge reset)
if(reset) if(reset)
begin begin
tx_packet[PW-1:0] <= 'b0; tx_packet[PW-1:0] <= 'b0;
tx_access <= 1'b0; tx_access <= 1'b0;
tx_burst <= 1'b0;//TODO
end end
else if(~tx_io_wait) else if(~tx_io_wait)
begin begin
tx_packet[PW-1:0] <= etx_packet[PW-1:0]; tx_packet[PW-1:0] <= etx_packet[PW-1:0];
tx_access <= etx_valid; tx_access <= etx_valid;
tx_burst <= 1'b0;//TODO
end end
//#############################
//# Burst Detection
//#############################
packet2emesh p2m1 (.access_out (last_access),
.write_out (last_write),
.datamode_out (last_datamode[1:0]),
.ctrlmode_out (last_ctrlmode[3:0]),
.dstaddr_out (last_dstaddr[31:0]),
.data_out (),
.srcaddr_out (),
.packet_in (tx_packet[PW-1:0]));//input
assign burst_addr[31:0] = last_dstaddr[31:0]+ 4'd8;
assign burst_type_match = {last_ctrlmode[3:0],last_datamode[1:0],last_write}
==
{etx_ctrlmode[3:0],etx_datamode[1:0], etx_write};
assign tx_burst = etx_write & //write
(etx_datamode[1:0]==2'b11) & //double only
burst_type_match & //same types
(burst_addr[31:0]==etx_dstaddr[31:0]); //inc by 8
//############################# //#############################
//# Wait signals (async) //# Wait signals (async)
//############################# //#############################
@ -124,13 +141,8 @@ endmodule // etx_protocol
// End: // End:
/* /*
File: etx_protocol.v
This file is part of the Parallella Project.
Copyright (C) 2014 Adapteva, Inc. Copyright (C) 2014 Adapteva, Inc.
Contributed by Fred Huettig <fred@adapteva.com> Contributed by Andreas Olofsson <andreas@adapteva.com>
Contributed by Andreas Olofsson <andreas@adapteva.com>
This program is free software: you can redistribute it and/or modify This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by it under the terms of the GNU General Public License as published by