FPGA/oh
1
0
Fork 0
mirror of https://github.com/aolofsson/oh.git synced 2025-01-30 02:32:53 +08:00
Code Issues Projects Releases Wiki Activity

Reorganizing readme for ease of use

Browse Source
This commit is contained in:
Andreas Olofsson 2016-02-16 13:25:58 -05:00
parent 54dcf478fe
commit d33f7f3c17
1 changed files with 37 additions and 34 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

71
chip/README.md
View File

@ -1,40 +1,18 @@
CHIP DESIGN REFERENCE FLOW
=======================================
This folder contains the recommended directory structure for implementing ASICs using OH! The directory structure is based on two decades of chip design experience (from 0.35um to 14nm) and is currently being used by Adapteva to design Epiphany based ASICs.
This folder contains a recommended reference flow for implementing chips using OH!
The structure is designed to simplify implementation scripts and maximize portability across:
* multiple foundries
* multiple process nodes
* multiple IP vendors
* multiple EDA vendors
## Flow Reference Guides
## RESOURCES
* [Synthesis](synthesis/README.md)
* [Place & Route](pnr/README.md)
* [Signoff](signoff/README.md)
## Other Resources
* [Glossary](docs/glossary.md)
* [Constants](docs/constants.md)
## DIRECTORY STRUCTURE & NAMING METHODOLOGY
| DIRECTORY NAME | DESCRIPTION |
|----------------------------|-----------------------------------------------|
| docs | open source documents and design guidelines |
| synthesis | open source synthesis scripts |
| pnr | open source place & route scripts |
| signoff | open source signoff scripts |
| eda | eda proprietary scripts |
| foundry ("foundry1") | tsmc, gf, tower, smic, umc, etc |
| process ("process1") | 28slp, 65g, etc |
| IP types("ip1") | pdk, stdlib, io, sram, serdes, etc |
| IP company name ("ipco1")| arm, synopsys, cadence, tsmc, etc |
| eda company name ("eda1")| synopsys, cadence, mentor, etc |
| proprietary | content under NDA not for distribution |
![alt tag](docs/directory_structure.png)
Description of contents inside each folder can be found in the local README.md file.
To visualize the directory structure, use the 'tree' utility.
## Required Shell Variables
| SHELL VARIABLE | DESCRIPTION |
@ -56,6 +34,36 @@ To visualize the directory structure, use the 'tree' utility.
| $OH_FLOORPLAN | Floorplanning file (tcl) |
| $OH_CONSTRAINTS | Timing constraints file |
## DIRECTORY STRUCTURE & NAMING METHODOLOGY
The structure is designed to simplify implementation scripts and maximize portability across:
* multiple foundries
* multiple process nodes
* multiple IP vendors
* multiple EDA vendors
| DIRECTORY NAME | DESCRIPTION |
|----------------------------|-----------------------------------------------|
| docs | open source documents and design guidelines |
| synthesis | open source synthesis scripts |
| pnr | open source place & route scripts |
| signoff | open source signoff scripts |
| eda | eda proprietary scripts |
| foundry ("foundry1") | tsmc, gf, tower, smic, umc, etc |
| process ("process1") | 28slp, 65g, etc |
| IP types("ip1") | pdk, stdlib, io, sram, serdes, etc |
| IP company name ("ipco1")| arm, synopsys, cadence, tsmc, etc |
| eda company name ("eda1")| synopsys, cadence, mentor, etc |
| proprietary | content under NDA not for distribution |
![alt tag](docs/directory_structure.png)
Description of contents inside each folder can be found in the local README.md file.
To visualize the directory structure, use the 'tree' utility.
## Example Design
```tcl
@ -89,10 +97,5 @@ set OH_FLOORPLAN ${OH_DESIGN}_floorplan.tcl
```
## Flow Reference Guides
* [Synthesis](synthesis/README.md)
* [Place & Route](pnr/README.md)
* [Signoff](signoff/README.md)