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Fixing priority on etx_arbiter
- don't do a combinatorial loopback on wait in a primitive cell, just bad practice... - changed priority to give readback priority over read, safer?
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@ -5,7 +5,7 @@
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module oh_arbiter_static(/*AUTOARG*/
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// Outputs
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grants, waits,
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grants,
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// Inputs
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requests
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);
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@ -14,7 +14,6 @@ module oh_arbiter_static(/*AUTOARG*/
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input [N-1:0] requests; //request vector
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output [N-1:0] grants; //grant (one hot)
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output [N-1:0] waits; //wait mask!
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genvar j;
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wire [N-1:0] waitmask;
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@ -28,7 +27,6 @@ module oh_arbiter_static(/*AUTOARG*/
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//grant circuit
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assign grants[N-1:0] = requests[N-1:0] & ~waitmask[N-1:0];
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assign waits[N-1:0] = requests[N-1:0] & ~grants[N-1:0];
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endmodule // oh_arbiter_priority
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@ -71,10 +71,7 @@ module etx_arbiter (/*AUTOARG*/
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wire [PW-1:0] etx_packet_mux;
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wire txrr_grant;
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wire txrd_grant;
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wire txwr_grant;
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wire txrr_arb_wait;
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wire txrd_arb_wait;
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wire txwr_arb_wait;
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wire txwr_grant;
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wire [PW-1:0] txrd_splice_packet;
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wire [PW-1:0] txwr_splice_packet;
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wire [PW-1:0] etx_mux;
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@ -106,10 +103,6 @@ module etx_arbiter (/*AUTOARG*/
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txrd_grant,
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txwr_grant //highest priority
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}),
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.waits({txrr_arb_wait,
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txrd_arb_wait,
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txwr_arb_wait
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}),
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.requests({txrr_access,
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txrd_access,
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txwr_access
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@ -130,17 +123,19 @@ module etx_arbiter (/*AUTOARG*/
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etx_rd_wait |
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etx_cfg_wait;
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//Host read request (self throttling, one read at a time)
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assign txrd_wait = etx_rd_wait |
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etx_wr_wait |
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etx_cfg_wait |
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txrd_arb_wait;
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//Read response
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assign txrr_wait = etx_wr_wait |
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etx_rd_wait |
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etx_cfg_wait |
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txrr_arb_wait;
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txwr_access;
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//Host read request (self throttling, one read at a time)
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assign txrd_wait = etx_rd_wait |
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etx_wr_wait |
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etx_cfg_wait |
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txrr_access |
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txwr_access;
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//#####################################################################
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//# Pipeline stage (arbiter+mux takes time..)
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//#####################################################################
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