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DV cleanup

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-Set VCO_MULT to 1 for PLL. Dirty hack to allow the RX clk to phase align with the input. Otherwise, if you multiply the VCO clock and then divide, you get a random phase alignment the way the current clock divider is written.
-Changed the fifo_cdc to 32 entries. Forgot that I had changed the fifo_cdc to hard coded per number of entries. Really need to have a parametrixed model that works!!
This commit is contained in:
Andreas Olofsson 2015-09-14 21:58:52 -04:00
parent 0415b01753
commit d7508f9938
2 changed files with 21 additions and 8 deletions
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18
elink/dv/dv_elink.v
View File

@ -276,6 +276,8 @@ module dv_elink(/*AUTOARG*/
.elink_en (elink0_elink_en), // Templated
.rx_clkin (elink0_rx_lclk_pll)); // Templated
defparam elink1_eclocks.PLL_VCO_MULT = 1; //needed to align clocks for RX
eclocks elink1_eclocks (.sys_clk (clk),
.e_cclk_p (),
.e_cclk_n (),
@ -636,8 +638,8 @@ module dv_elink(/*AUTOARG*/
wire elink_axi_access;
wire [PW-1:0] elink_axi_packet;
defparam axi_fifo.DW=104;
defparam axi_fifo.DEPTH=64;
defparam axi_fifo.DW = 104;
defparam axi_fifo.DEPTH = 32; //TODO: fix the model, only 16/32 allowed!
fifo_cdc axi_fifo(
// Outputs
.wait_out (),
@ -808,8 +810,8 @@ module dv_elink(/*AUTOARG*/
wire elink2_access;
wire [PW-1:0] elink2_packet;
defparam model_fifo.DW=104;
defparam model_fifo.DEPTH=64;
defparam model_fifo.DW = 104;
defparam model_fifo.DEPTH = 32;
fifo_cdc model_fifo(
// Outputs
.wait_out (),
@ -822,7 +824,7 @@ module dv_elink(/*AUTOARG*/
.reset_out (reset),
.access_in (ext_access),
.packet_in (ext_packet[PW-1:0]),
.wait_in (elink2_wait_out)
.wait_in (1'b0)//elink2_wait_out
);
elink_e16 elink_ref (
@ -847,9 +849,9 @@ module dv_elink(/*AUTOARG*/
.c1_clk_in (clk),
.c2_clk_in (clk),
.c3_clk_in (clk),
.rxi_data (elink0_txo_data_p[7:0]),
.rxi_lclk (elink0_txo_lclk_p),
.rxi_frame (elink0_txo_frame_p),
.rxi_data (8'b0),
.rxi_lclk (1'b0),
.rxi_frame (1'b0),
.txo_rd_wait (1'b0),
.txo_wr_wait (1'b0),
.c0_mesh_access_in (elink2_access),

11
elink/dv/test.memh
View File

@ -28,3 +28,14 @@
810D0060_DEADBEEF_80800060_09 //read
810D0068_DEADBEEF_80800068_09 //read
810D0070_DEADBEEF_80800070_09 //read
B7B6B5B4_B3B2B1B0_80800100_0f //write to epiphany
C7C6C5C4_C3C2C1C0_80800108_0f //write to epiphany
D7D6D5D4_D3D2D1D0_80800110_0f //write to epiphany
E7E6E5E4_E3E2E1E0_80800118_0f //write to epiphany
F7F6F5F4_F3F2F1F0_80800120_0f //write to epiphany
810D0100_DEADBEEF_80800100_0d //read
810D0108_DEADBEEF_80800108_0d //read
810D0108_DEADBEEF_80800110_0d //read
810D0118_DEADBEEF_80800118_0d //read
810D0120_DEADBEEF_80800120_0d //read
00000000_00000000_00000000_00 //END OF BURST