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Writing while full is aserted

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This commit is contained in:
Andreas Olofsson 2015-08-14 17:15:38 -04:00
parent 9bc40a8355
commit d81bb66d73
1 changed files with 3 additions and 3 deletions
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6
memory/hdl/fifo_cdc.v
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@ -21,7 +21,7 @@ module fifo_cdc (/*AUTOARG*/
input clk_in;
input reset_in;
input access_in;
input [DW-1:0] packet_in;
input [DW-1:0] packet_in;
output wait_out;
/********************************/
@ -30,7 +30,7 @@ module fifo_cdc (/*AUTOARG*/
input clk_out;
input reset_out;
output access_out;
output [DW-1:0] packet_out;
output [DW-1:0] packet_out;
input wait_in;
//Local wires
@ -41,7 +41,7 @@ module fifo_cdc (/*AUTOARG*/
wire valid;
reg access_out;
assign wr_en = access_in & ~full;
assign wr_en = access_in;//&~full
assign rd_en = ~empty & ~wait_in;
assign wait_out = full;