FPGA/oh
1
0
Fork 0
mirror of https://github.com/aolofsson/oh.git synced 2025-02-07 06:44:09 +08:00
Code Issues Projects Releases Wiki Activity

Writing while full is aserted

Browse Source
This commit is contained in:
Andreas Olofsson 2015-08-14 17:15:38 -04:00
parent 9bc40a8355
commit d81bb66d73
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
memory/hdl/fifo_cdc.v
View File

@ -41,7 +41,7 @@ module fifo_cdc (/*AUTOARG*/
wire valid;
reg access_out;
assign wr_en = access_in & ~full;
assign wr_en = access_in;//&~full
assign rd_en = ~empty & ~wait_in;
assign wait_out = full;