diff --git a/stdlib/hdl/oh_fifo_sync.v b/stdlib/hdl/oh_fifo_sync.v
index 112e3a7..fbd7614 100644
--- a/stdlib/hdl/oh_fifo_sync.v
+++ b/stdlib/hdl/oh_fifo_sync.v
@@ -62,12 +62,12 @@ module oh_fifo_sync
    // FIFO Control
    //#########################################################
 
-   assign fifo_read   = rd_en & ~rd_empty;
-   assign fifo_write  = wr_en & ~wr_full;
-   assign almost_full = (wr_count[AW-1:0] == PROGFULL);
-   assign ptr_match   = (wr_addr[AW-1:0] == rd_addr[AW-1:0]);
-   assign full        = ptr_match & (wr_addr[AW]==!rd_addr[AW]);
-   assign fifo_empty  = ptr_match & (wr_addr[AW]==rd_addr[AW]);
+   assign fifo_read      = rd_en & ~rd_empty;
+   assign fifo_write     = wr_en & ~wr_full;
+   assign wr_almost_full = (wr_count[AW-1:0] == PROGFULL);
+   assign ptr_match      = (wr_addr[AW-1:0] == rd_addr[AW-1:0]);
+   assign wr_full        = ptr_match & (wr_addr[AW]==!rd_addr[AW]);
+   assign rd_empty       = ptr_match & (wr_addr[AW]==rd_addr[AW]);
 
    always @ (posedge clk or negedge nreset)
      if(~nreset)
diff --git a/stdlib/hdl/oh_mux4.v b/stdlib/hdl/oh_mux4.v
index 252cb9b..48c8e7b 100644
--- a/stdlib/hdl/oh_mux4.v
+++ b/stdlib/hdl/oh_mux4.v
@@ -7,10 +7,10 @@
 
 module oh_mux4 #(parameter N = 1 ) // width of mux
    (
-    input 	    sel3,
-    input 	    sel2,
-    input 	    sel1,
-    input 	    sel0,
+    input 	   sel3,
+    input 	   sel2,
+    input 	   sel1,
+    input 	   sel0,
     input [N-1:0]  in3,
     input [N-1:0]  in2,
     input [N-1:0]  in1,
@@ -19,9 +19,9 @@ module oh_mux4 #(parameter N = 1 ) // width of mux
     );
 
    assign out[N-1:0] = ({(N){sel0}} & in0[N-1:0] |
-			 {(N){sel1}} & in1[N-1:0] |
-			 {(N){sel2}} & in2[N-1:0] |
-			 {(N){sel3}} & in3[N-1:0]);
+			{(N){sel1}} & in1[N-1:0] |
+			{(N){sel2}} & in2[N-1:0] |
+			{(N){sel3}} & in3[N-1:0]);
 
 `ifdef TARGET_SIM
    wire 	    error;