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Fixing old WIP typo bug

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aolofsson 2022-05-29 08:43:44 -04:00
parent 818ad00d3c
commit d8b44971b5
2 changed files with 13 additions and 13 deletions
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12
stdlib/hdl/oh_fifo_sync.v
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@ -62,12 +62,12 @@ module oh_fifo_sync
// FIFO Control // FIFO Control
//######################################################### //#########################################################
assign fifo_read = rd_en & ~rd_empty; assign fifo_read = rd_en & ~rd_empty;
assign fifo_write = wr_en & ~wr_full; assign fifo_write = wr_en & ~wr_full;
assign almost_full = (wr_count[AW-1:0] == PROGFULL); assign wr_almost_full = (wr_count[AW-1:0] == PROGFULL);
assign ptr_match = (wr_addr[AW-1:0] == rd_addr[AW-1:0]); assign ptr_match = (wr_addr[AW-1:0] == rd_addr[AW-1:0]);
assign full = ptr_match & (wr_addr[AW]==!rd_addr[AW]); assign wr_full = ptr_match & (wr_addr[AW]==!rd_addr[AW]);
assign fifo_empty = ptr_match & (wr_addr[AW]==rd_addr[AW]); assign rd_empty = ptr_match & (wr_addr[AW]==rd_addr[AW]);
always @ (posedge clk or negedge nreset) always @ (posedge clk or negedge nreset)
if(~nreset) if(~nreset)

14
stdlib/hdl/oh_mux4.v
View File

@ -7,10 +7,10 @@
module oh_mux4 #(parameter N = 1 ) // width of mux module oh_mux4 #(parameter N = 1 ) // width of mux
( (
input sel3, input sel3,
input sel2, input sel2,
input sel1, input sel1,
input sel0, input sel0,
input [N-1:0] in3, input [N-1:0] in3,
input [N-1:0] in2, input [N-1:0] in2,
input [N-1:0] in1, input [N-1:0] in1,
@ -19,9 +19,9 @@ module oh_mux4 #(parameter N = 1 ) // width of mux
); );
assign out[N-1:0] = ({(N){sel0}} & in0[N-1:0] | assign out[N-1:0] = ({(N){sel0}} & in0[N-1:0] |
{(N){sel1}} & in1[N-1:0] | {(N){sel1}} & in1[N-1:0] |
{(N){sel2}} & in2[N-1:0] | {(N){sel2}} & in2[N-1:0] |
{(N){sel3}} & in3[N-1:0]); {(N){sel3}} & in3[N-1:0]);
`ifdef TARGET_SIM `ifdef TARGET_SIM
wire error; wire error;