diff --git a/elink/README.md b/elink/README.md
index c8f1a0e..4528e3b 100644
--- a/elink/README.md
+++ b/elink/README.md
@@ -93,8 +93,8 @@ B05      | {dstaddr[3:0],datamode[1:0],write,access}
 +B06     | data[31:24] / srcaddr[31:24]
 +B07     | data[23:16] / srcaddr[23:16]
 +B08     | data[15:8] / srcaddr[15:8]
-+B09     | data[7:0] / srcaddr[7:0]
-++B10    | data[63:56]  
+++B09    | data[7:0] / srcaddr[7:0]
+B10      | data[63:56]  
 B11      | data[55:48]  
 B12      | data[47:40]  
 B13      | data[39:32]  
diff --git a/elink/dv/elink.cmd b/elink/dv/elink.cmd
index 6c8f7d3..27b076c 100644
--- a/elink/dv/elink.cmd
+++ b/elink/dv/elink.cmd
@@ -8,6 +8,7 @@ elink_e16_model.v
 -y ../../common/hdl
 -y ../../memory/hdl
 -y ../../emailbox/hdl
+-y ../../emesh/hdl
 -y ../../emmu/hdl
 -y ../../edma/hdl
 
diff --git a/elink/dv/test.memh b/elink/dv/test.memh
index e5351ed..5c91085 100644
--- a/elink/dv/test.memh
+++ b/elink/dv/test.memh
@@ -1,32 +1,5 @@
-00000000_00000000_00000000_00 //***START OF TX REGS***
-00000000_00000001_810e000c_0b //ELRESET
-00000000_00000000_810e000c_0b //ELRESET
-00000000_00000331_810e0010_0b //ELCLK
-00000000_00000001_810e0000_0b //ELTXCFG
-00000000_00000001_810e0004_0b //ELTXSTATUS
-00000000_FFFFFFFF_810e0008_0b //ELTXGPIO
-00000000_AAAAAAAA_810e0014_0b //ELCHIPID
-00000000_BBBBBBBB_810e0018_0b //ELVERSION
-00000000_808CCCCC_810e0020_0b //ELTXDSTADDR
-00000000_DDDDDDDD_810e0024_0b //ELTXDATA
-00000000_810d0014_810e0028_0b //ELTXSRCADDR
-00000000_0000000b_810e001c_0b //ELTXTEST
-00000000_00000000_00000000_00 //WAIT
-00000000_00000000_00000000_00 //WAIT
-00000000_00000000_00000000_00 //WAIT
-00000000_00000810_810ec080_0b //ETXMMU
-00000000_00000000_00000000_00 //***END OF TX REGS***
-00000000_00000001_810d0000_0b //ELRXCFG
-00000000_00000001_810d0004_0b //ELRXSTATUS
-00000000_AAAAAAAA_810d0008_0b //ELRXGPIO
-00000000_BBBBBBBB_810d0014_0b //ELRXRR
-00000000_CCCCCCCC_810d0018_0b //ELRXBASE
-00000000_DDDDDDDD_810d0020_0b //ELMAILBOXLO
-00000000_EEEEEEEE_810d0020_0b //ELMAILBOXHI
-00000000_00000213_810d0024_0b //EDMACFG
-00000000_00000000_810d0028_0b //EDMACOUNT
-00000000_00000000_810d0028_0b //EDMASTRIDE
-00000000_00000000_810d0028_0b //EDMASTRIDE
-00000000_00000000_810d0028_0b //EDMASRCADDR
-00000000_00000000_810d0028_0b //EDMADSTADDR
-00000000_00000810_810dc080_0b //ERXMMU
+B7B6B5B4_B3B2B1B0_80800000_0f //write to epiphany
+C7C6C5C4_C3C2C1C0_80800008_0f //write to epiphany
+D7D6D5D4_D3D2D1D0_80800010_0f //write to epiphany
+E7E6E5E4_E3E2E1E0_80800018_0f //write to epiphany
+F7F6F5F4_F3F2F1F0_80800020_0f //write to epiphany
diff --git a/elink/hdl/ecfg_if.v b/elink/hdl/ecfg_if.v
index b03ef43..0229da6 100644
--- a/elink/hdl/ecfg_if.v
+++ b/elink/hdl/ecfg_if.v
@@ -159,11 +159,11 @@ module ecfg_if (/*AUTOARG*/
    emesh2packet e2p (.packet_out	(packet_out[PW-1:0]),
 		     .access_in		(1'b1),
 		     .write_in		(write_reg),
-		     .datamode_in	(datamode_reg[1:0]),
-		     .ctrlmode_in	(ctrlmode_reg[3:0]),
-		     .dstaddr_in	(dstaddr_reg[AW-1:0]),
+		     .datamode_in        (datamode_reg[1:0]),
+		     .ctrlmode_in   	(ctrlmode_reg[3:0]),
+		     .dstaddr_in   	(dstaddr_reg[AW-1:0]),
 		     .data_in		(data_out[31:0]),
-		     .srcaddr_in	(srcaddr_reg[AW-1:0])
+		     .srcaddr_in        (srcaddr_reg[AW-1:0])
 		     );
    
    
diff --git a/elink/hdl/elink.v b/elink/hdl/elink.v
index 20b5878..0676ca5 100644
--- a/elink/hdl/elink.v
+++ b/elink/hdl/elink.v
@@ -22,13 +22,13 @@ module elink(/*AUTOARG*/
    /****************************/
    /*CLK AND RESET             */
    /****************************/
-   input        reset;               // active high asynchronous hardware reset
-   input 	clkin;               // pll input clock
-   input 	sys_clk;             // system clock for FIFOs only
-   input [3:0] 	pll_bypass;          // pll bypass clocks for elink   
-   input 	testmode;            // places elink in testmode
-   output 	rx_lclk_div4;        // rx clock for synching with logic
-   output 	tx_lclk_div4;        // tx clock for synching with logic
+   input        reset;            // active high async reset
+   input 	clkin;            // pll input clock
+   input 	sys_clk;          // system clock for FIFOs only
+   input [3:0] 	pll_bypass;       // pll bypass clocks for elink   
+   input 	testmode;         // places elink in testmode
+   output 	rx_lclk_div4;     // rx clock for synching with logic
+   output 	tx_lclk_div4;     // tx clock for synching with logic
 
    /********************************/
    /*ELINK I/O PINS                */
diff --git a/elink/hdl/erx_protocol.v b/elink/hdl/erx_protocol.v
index 4961bac..ec61a96 100644
--- a/elink/hdl/erx_protocol.v
+++ b/elink/hdl/erx_protocol.v
@@ -336,11 +336,11 @@ module erx_protocol (/*AUTOARG*/
 		     // Inputs
 		     .access_in		(erx_access),
 		     .write_in		(write_reg),
-		     .datamode_in	(datamode_reg[1:0]),
-		     .ctrlmode_in	(ctrlmode_reg[3:0]),
-		     .dstaddr_in	(dstaddr_reg[AW-1:0]),
+		     .datamode_in       (datamode_reg[1:0]),
+		     .ctrlmode_in       (ctrlmode_reg[3:0]),
+		     .dstaddr_in        (dstaddr_reg[AW-1:0]),
 		     .data_in		(data_reg[DW-1:0]),
-		     .srcaddr_in	(srcaddr_reg[AW-1:0])
+		     .srcaddr_in        (srcaddr_reg[AW-1:0])
 		     );
    
    //dont't remap read returns and writes to RX registers