mirror of
https://github.com/aolofsson/oh.git
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DV cleanup
-removing all redundant build files, there must be only one...
This commit is contained in:
Andreas Olofsson
parent
2ef626b91a
commit
d9f18e7b58
19
README.md
19
README.md
@ -41,10 +41,27 @@
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```sh
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./build.sh gpio/dv/dut_gpio.v # compile gpio testbench (example)
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./sim.sh gpio/dv/tests/test_regs.emf # run a simulation with "test_regs.emf"
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./sim.sh gpio/dv/tests/test_basic.emf # run a simulation with "test_regs.emf"
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./view.sh # open the waveform with gtkwave
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```
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**Short-cut:**
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* Builds $name/dv/dut_$name.v
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* Runs test $name/dv/tests/test_basic.emf
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```sh
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./run.sh accelerator
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./run.sh elink
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./run.sh emailbox
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./run.sh emmu
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./run.sh gpio
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./run.sh spi
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./run.sh pic
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```
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## LICENSE
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The OH! repository source code is licensed under the MIT license unless otherwise specified. See [LICENSE](LICENSE) for MIT copyright terms. Design specific licenses can be found in the folder root (eg: aes/LICENSE)
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@ -1,13 +0,0 @@
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#!/bin/bash
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dut="axi_accelerator"
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top="../../common/dv/dv_top.v"
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iverilog -g2005 -DTARGET_SIM=1 -DTARGET_XILINX=1 $top dut_${dut}.v -f ../../common/dv/libs.cmd -o ${dut}.vvp $1
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#-Wtimescale
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#PUT TARGET_SIM
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#-pfileline=1
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#-Wall
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@ -1,9 +1,9 @@
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`include "elink_regmap.v"
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//`include "elink_regmap.v"
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module dut(/*AUTOARG*/
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// Outputs
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dut_active, wait_out, access_out, packet_out,
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dut_active, clkout, wait_out, access_out, packet_out,
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// Inputs
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clk, nreset, vdd, vss, access_in, packet_in, wait_in
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clk1, clk2, nreset, vdd, vss, access_in, packet_in, wait_in
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);
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//##########################################################################
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@ -18,11 +18,13 @@ module dut(/*AUTOARG*/
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parameter N = 1;
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//clock,reset
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input clk;
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input clk1;
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input clk2;
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input nreset;
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input [N*N-1:0] vdd;
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input vss;
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output dut_active;
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output clkout;
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//Stimulus Driven Transaction
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input [N-1:0] access_in;
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@ -127,13 +129,16 @@ module dut(/*AUTOARG*/
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wire s_axi_wvalid; // From emaxi of emaxi.v
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// End of automatics
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assign clkout = clk1;
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assign dut_active = 1'b1;
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//######################################################################
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//ACCELERATOR
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//######################################################################
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axi_accelerator
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axi_accelerator (.sys_nreset (nreset),
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.sys_clk (clk),
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.sys_clk (clk1),
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.m_axi_aresetn (nreset),
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.s_axi_aresetn (nreset),
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.s_axi_wstrb (s_axi_wstrb[7:4] | s_axi_wstrb[3:0]),
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@ -231,7 +236,7 @@ module dut(/*AUTOARG*/
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*/
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emaxi #(.M_IDW(M_IDW))
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emaxi (.m_axi_aclk (clk),
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emaxi (.m_axi_aclk (clk1),
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.m_axi_aresetn (nreset),
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.m_axi_rdata ({s_axi_rdata[31:0],s_axi_rdata[31:0]}),
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.rr_wait (wait_in),
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@ -286,7 +291,7 @@ module dut(/*AUTOARG*/
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assign dut_active = 1'b1;
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//Tie off master output for now
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@ -294,7 +299,7 @@ module dut(/*AUTOARG*/
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);
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*/
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axislave_stub m_stub (.s_axi_aclk (clk),
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axislave_stub m_stub (.s_axi_aclk (clk1),
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.s_axi_aresetn (nreset),
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/*AUTOINST*/
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// Outputs
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@ -1,7 +0,0 @@
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#!/bin/bash
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if [ -e "test_0.emf" ]
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then
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rm test_0.emf
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fi
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cp $1 test_0.emf
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./axi_accelerator.vvp
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@ -1,5 +0,0 @@
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DEADBEEF_00000001_810f0000_05_0010 //INPUT A
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DEADBEEF_00000002_810f0004_05_0010 //INPUT B
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00000000_DEADBEEF_810f0008_04_0010 //READ OUTPUT
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@ -1,27 +0,0 @@
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#!/bin/bash
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############################################################################
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# Icarus Verilog build script for OH!
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# Requires $OH_HOME variable to be set
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############################################################################
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DUT=$1
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#Create directory of all links
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mkdir -p $OH_HOME/symlinks/hdl
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mkdir -p $OH_HOME/symlinks/dv
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pushd $OH_HOME/symlinks/hdl
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ln -s ../../*/hdl/*.v .
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cd ../dv
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ln -s ../../*/dv/*.v .
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popd
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exit
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#Build
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iverilog -g2005\
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-DTARGET_SIM=1\
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$DUT\
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$OH_HOME/symlinks/dv/dv_top.v\
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-y .\
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-y $OH_HOME/symlinks/hdl\
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-y $OH_HOME/symlinks/dv\
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-I $OH_HOME/symlinks/hdl
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-o dut.bin\
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@ -1,13 +0,0 @@
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#!/bin/bash
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# Compiles all dut*.v files in this directory
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DV=../../common/dv/dv_top.v
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LIBS=$OH_HOME/common/dv/libs.cmd
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CFG="cfg_random.v"
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for file in dut*.v
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do
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root=${file%%.*}
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iverilog -g2005 -DTARGET_SIM=1 $CFG $file $DV -f $LIBS -o $root.bin
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done
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@ -1,119 +0,0 @@
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//`timescale 1 ns / 100 ps
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module dv_embox();
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parameter DW = 32;
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//Stimulus to drive
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reg clk;
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reg reset;
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reg mi_access;
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reg [19:0] mi_addr;
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reg [31:0] mi_data_in;
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reg mi_write;
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reg [1:0] test_state;
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reg go;
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//Reset
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initial
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begin
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$display($time, " << Starting the Simulation >>");
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#0
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clk = 1'b0; // at time 0
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reset = 1'b1; // reset is active
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mi_write = 1'b0;
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mi_access = 1'b0;
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mi_addr[19:0] = 20'hf0368;
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mi_data_in[31:0] = 32'h0;
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test_state[1:0] = 2'b00;
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go = 1'b0;
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#100
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reset = 1'b0; // at time 100 release reset
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#100
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go = 1'b1;
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#10000
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$finish;
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end
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//Clock
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always
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#10 clk = ~clk;
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//Pattern generator
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//1.) Write in 8 transactions (split into low and high)
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//2.) Read back 8 transactions (split into low and high)
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always @ (negedge clk)
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if(go)
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begin
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case(test_state[1:0])
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2'b00://write
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if(~done)
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begin
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mi_access <= 1'b1;
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mi_write <= 1'b1;
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mi_addr[19:0] <= mi_addr[19:0] ^ 20'hc;
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mi_data_in[31:0] <= mi_data_in[31:0]+1'b1;
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end
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else
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begin
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test_state <= 2'b01;
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mi_addr[19:0] <= 20'hf0368;
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mi_data_in[31:0] <= 32'h0;
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end
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2'b01://read
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if(~done)
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begin
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mi_write <= 1'b0;
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mi_access <= 1'b1;
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mi_addr[19:0] <= mi_addr[19:0] ^ 20'hc;
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mi_data_in[31:0] <= mi_data_in[31:0]+1'b1;
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end
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else
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begin
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test_state <= 2'b10;
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mi_write <= 1'b0;
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mi_access <= 1'b0;
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end
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endcase // case (test_state[1:0])
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end
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wire done = (mi_data_in[19:0]==20'h8);
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire embox_empty; // From embox of embox.v
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wire embox_full; // From embox of embox.v
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wire [DW-1:0] mi_data_out; // From embox of embox.v
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// End of automatics
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//DUT
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embox embox(
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/*AUTOINST*/
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// Outputs
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.mi_data_out (mi_data_out[DW-1:0]),
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.embox_full (embox_full),
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.embox_empty (embox_empty),
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// Inputs
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.reset (reset),
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.clk (clk),
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.mi_access (mi_access),
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.mi_write (mi_write),
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.mi_addr (mi_addr[19:0]),
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.mi_data_in (mi_data_in[DW-1:0]));
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//Waveform dump
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initial
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begin
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$dumpfile("test.vcd");
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$dumpvars(0, dv_embox);
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end
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endmodule // dv_embox
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// Local Variables:
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// verilog-library-directories:("." "../hdl" "../../memory/hdl ")
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// End:
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@ -1,10 +0,0 @@
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#!/bin/bash
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#Compiling sim
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iverilog -y ../../fifos/hdl/ \
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-y ../../common/hdl \
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-y ../../memory/hdl \
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-y ../hdl \
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dv_embox.v
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#Running sim
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./a.out
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@ -1,149 +0,0 @@
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//`timescale 1 ns / 100 ps
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module dv_emmu
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(input clk,
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input reset,
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input go);
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parameter DW = 32; //data width of
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parameter AW = 32; //data width of
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parameter IW = 12; //index size of table
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parameter PAW = 64; //physical address width of output
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parameter MW = PAW-AW+IW; //table data width
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parameter MD = 1<<IW; //memory depth
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//Stimulus to drive
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reg mmu_en;
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//Reg interface
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reg mi_en;
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reg [12:0] mi_addr;
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reg [31:0] mi_din;
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reg [3:0] mi_we;
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//emesh interface
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reg emesh_access_in;
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reg emesh_write_in;
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reg [1:0] emesh_datamode_in;
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reg [3:0] emesh_ctrlmode_in;
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reg [AW-1:0] emesh_dstaddr_in;
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reg [AW-1:0] emesh_srcaddr_in;
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reg [DW-1:0] emesh_data_in;
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//Test junk
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reg [1:0] test_state;
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//Pattern generator
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//1.) Write some patterns through mi_interface
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//2.) Write some patterns from emesh interface
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always @ (negedge clk) begin
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if(go)
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begin
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case(test_state[1:0])
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2'b00://write entries
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if(mi_addr[12:0]<13'h16)
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begin
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mi_en <= 1'b1;
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mi_we[3:0] <= 4'b1111;
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mi_addr[12:0] <= mi_addr[12:0] + 1'b1;
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/* verilator lint_off WIDTH */
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mi_din[31:0] <= mi_addr[0] ? (mi_addr[12:0]+32'hFFFFF000) : 32'hFFFFFFFF;
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/* verilator lint_on WIDTH */
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end
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else
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begin
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test_state <= 2'b01;
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mi_en <= 1'b0;
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end
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2'b01://
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if(emesh_dstaddr_in[31:0]<32'h00800000)
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begin
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emesh_access_in <= 1'b1;
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emesh_write_in <= 1'b1;
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emesh_dstaddr_in[31:0] <= emesh_dstaddr_in[31:0] + 32'h00100001;
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emesh_ctrlmode_in[3:0] <= 4'b1111;
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emesh_datamode_in[1:0] <= 2'b11;
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emesh_data_in[31:0] <= 32'h12345678;
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emesh_srcaddr_in[31:0] <= 32'h55555555;
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end
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else
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begin
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test_state <= 2'b10;
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emesh_access_in <= 1'b0;
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end // else: !if(~done)
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2'b10://init array
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begin
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mi_addr[5:0] <= mi_addr[5:0]-1'b1;
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end
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default : test_state <= test_state;
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endcase // case (test_state[1:0])
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end // if (go)
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if (reset) begin
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mi_we[3:0] <= 4'b0;
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mi_en <= 1'b0;
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mi_addr[12:0] <= 13'b0;
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mi_din[31:0] <= 32'h55555000;
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test_state[1:0] <= 2'b00;
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emesh_access_in <= 1'b0;
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emesh_write_in <= 1'b0;
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emesh_ctrlmode_in[3:0] <= 4'b0;
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emesh_datamode_in[1:0] <= 2'b0;
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emesh_dstaddr_in[31:0] <= 32'b0;
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emesh_srcaddr_in[31:0] <= 32'b0;
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emesh_data_in[31:0] <= 32'b0;
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mmu_en <= 1'b1;
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end
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end
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wire done = (mi_addr[5:0]==6'b001101);
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire emmu_access_out; // From emmu of emmu.v
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wire [3:0] emmu_ctrlmode_out; // From emmu of emmu.v
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wire [DW-1:0] emmu_data_out; // From emmu of emmu.v
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wire [1:0] emmu_datamode_out; // From emmu of emmu.v
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wire [63:0] emmu_dstaddr_out; // From emmu of emmu.v
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wire [AW-1:0] emmu_srcaddr_out; // From emmu of emmu.v
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wire emmu_write_out; // From emmu of emmu.v
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wire [31:0] mi_dout; // From emmu of emmu.v
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// End of automatics
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/*AUTOWIRE*/
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//DUT
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emmu emmu(.mi_clk (clk),
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/*AUTOINST*/
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// Outputs
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.mi_dout (mi_dout[31:0]),
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.emmu_access_out (emmu_access_out),
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.emmu_write_out (emmu_write_out),
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.emmu_datamode_out (emmu_datamode_out[1:0]),
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.emmu_ctrlmode_out (emmu_ctrlmode_out[3:0]),
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.emmu_dstaddr_out (emmu_dstaddr_out[63:0]),
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.emmu_srcaddr_out (emmu_srcaddr_out[AW-1:0]),
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.emmu_data_out (emmu_data_out[DW-1:0]),
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// Inputs
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.clk (clk),
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.mmu_en (mmu_en),
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.mi_en (mi_en),
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.mi_we (mi_we[3:0]),
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.mi_addr ({3'b000,mi_addr[12:0]}),
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.mi_din (mi_din[31:0]),
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.emesh_access_in (emesh_access_in),
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.emesh_write_in (emesh_write_in),
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.emesh_datamode_in (emesh_datamode_in[1:0]),
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.emesh_ctrlmode_in (emesh_ctrlmode_in[3:0]),
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.emesh_dstaddr_in (emesh_dstaddr_in[AW-1:0]),
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.emesh_srcaddr_in (emesh_srcaddr_in[AW-1:0]),
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.emesh_data_in (emesh_data_in[DW-1:0]));
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endmodule // dv_emmu
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// Local Variables:
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// verilog-library-directories:("." "../hdl")
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// End:
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@ -1,39 +0,0 @@
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module dv_emmu_tb;
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reg clk;
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reg reset;
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reg go;
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//Clock
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always
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#10 clk = ~clk;
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initial
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begin
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$display($time, " << Starting the Simulation >>");
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#0
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clk = 1'b0; // at time 0
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reset = 1'b1; // reset is active
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#100
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reset = 1'b0; // at time 100 release reset
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||||
#100
|
||||
go = 1'b1;
|
||||
#10000
|
||||
$finish;
|
||||
end
|
||||
|
||||
//Waveform dump
|
||||
initial
|
||||
begin
|
||||
$dumpfile("test.vcd");
|
||||
$dumpvars(0, dv_emmu);
|
||||
end
|
||||
|
||||
|
||||
dv_emmu dv_emmu
|
||||
(.clk (clk),
|
||||
.reset (reset),
|
||||
.go (go));
|
||||
endmodule
|
||||
@ -1,34 +0,0 @@
|
||||
#include <verilated.h>
|
||||
#include <verilated_vcd_c.h>
|
||||
|
||||
#include "Vdv_emmu__Syms.h"
|
||||
|
||||
int main(int argc, char **argv, char **env)
|
||||
{
|
||||
Verilated::commandArgs(argc, argv);
|
||||
|
||||
uint64_t t;
|
||||
|
||||
//VCD stuff
|
||||
Verilated::traceEverOn(true);
|
||||
VerilatedVcdC* tfp = new VerilatedVcdC;
|
||||
//char *vcdFileName;
|
||||
Vdv_emmu* top = new Vdv_emmu;
|
||||
top->trace(tfp, 99);
|
||||
tfp->open("test.vcd"/*vcdFileName*/);
|
||||
|
||||
//Init values
|
||||
top->clk = 0;
|
||||
top->reset = 1;
|
||||
top->go = 0;
|
||||
|
||||
while(t<100000) {
|
||||
if (t==100) top->reset = 0;
|
||||
if (t==10000) top->go = 1;
|
||||
top->eval();
|
||||
top->clk = !top->clk;
|
||||
tfp->dump((vluint64_t)t);
|
||||
t++;
|
||||
}
|
||||
tfp->close();
|
||||
}
|
||||
@ -1,10 +0,0 @@
|
||||
#!/bin/bash
|
||||
#Compiling sim
|
||||
iverilog -y ../../fifos/hdl/ \
|
||||
-y ../../common/hdl \
|
||||
-y ../../memory/hdl \
|
||||
-y ../hdl \
|
||||
dv_emmu.v
|
||||
|
||||
#Running sim
|
||||
./a.out
|
||||
@ -1,13 +0,0 @@
|
||||
#!/bin/bash
|
||||
|
||||
dut="etrace"
|
||||
top="../../common/dv/dv_top.v"
|
||||
iverilog -g2005 -DTARGET_SIM=1 -DTARGET_XILINX=1 $top dut_${dut}.v -f ../../common/dv/libs.cmd -o ${dut}.vvp $1
|
||||
|
||||
#-Wtimescale
|
||||
|
||||
#PUT TARGET_SIM
|
||||
|
||||
#-pfileline=1
|
||||
#-Wall
|
||||
|
||||
@ -1,7 +0,0 @@
|
||||
#!/bin/bash
|
||||
if [ -e "test_0.memh" ]
|
||||
then
|
||||
rm test_0.memh
|
||||
fi
|
||||
cp $1 test_0.memh
|
||||
./etrace.vvp
|
||||
@ -1,19 +0,0 @@
|
||||
00000000_00000001_810F0000_05_0010 //enable tracer
|
||||
00000001_00000000_00000001_05_0010 //s0:use source address and write to dummy
|
||||
10000000_00000000_00000001_05_0010 //s1
|
||||
10000000_00000000_00000001_05_0010 //s2
|
||||
00000000_00000000_00000001_05_0010 //s3
|
||||
11111111_00000000_00000001_05_0010 //s4
|
||||
00000000_00000000_810A0000_04_0010 //read sample0
|
||||
00000000_00000000_810A0004_04_0010 //
|
||||
00000000_00000000_810A0008_04_0010 //read sample1
|
||||
00000000_00000000_810A000c_04_0010 //
|
||||
00000000_00000000_810A0010_04_0010 //read sample2
|
||||
00000000_00000000_810A0014_04_0010 //
|
||||
00000000_00000000_810A0018_04_0010 //read sample3
|
||||
00000000_00000000_810A001c_04_0010 //
|
||||
00000000_00000000_810A0020_04_0010 //read sample4
|
||||
00000000_00000000_810A0024_04_0010 //
|
||||
|
||||
|
||||
|
||||
@ -1,16 +0,0 @@
|
||||
#!/bin/bash
|
||||
|
||||
DV="../../common/dv/dv_top.v"
|
||||
DUT="dut_gpio.v"
|
||||
ROOT="gpio"
|
||||
iverilog -o $ROOT.bin -g2005 -DTARGET_SIM=1 \
|
||||
$DV \
|
||||
$DUT \
|
||||
-y ../hdl \
|
||||
-y ../../common/hdl/ \
|
||||
-y ../../common/dv/ \
|
||||
-y ../../emesh/hdl/ \
|
||||
-y ../../emesh/dv/ \
|
||||
-I ../hdl
|
||||
|
||||
|
||||
@ -1,7 +0,0 @@
|
||||
#!/bin/bash
|
||||
if [ -e "test_0.emf" ]
|
||||
then
|
||||
rm test_0.emf
|
||||
fi
|
||||
cp $1 test_0.emf
|
||||
./gpio.bin
|
||||
@ -1,12 +0,0 @@
|
||||
#!/bin/bash
|
||||
|
||||
# Compiles all dut*.v files in this directory
|
||||
|
||||
DV=../../common/dv/dv_top.v
|
||||
DUT=dut_mio.v
|
||||
LIBS=$OH_HOME/common/dv/libs.cmd
|
||||
CFG="../hdl/cfg_mio.vh"
|
||||
|
||||
root=${DUT%%.*}
|
||||
iverilog -g2005 -DTARGET_SIM=1 $CFG $DUT $DV -f $LIBS -o $root.bin
|
||||
|
||||
@ -1,16 +0,0 @@
|
||||
#!/bin/bash
|
||||
|
||||
DV=../../common/dv/dv_top.v
|
||||
LIBS=$OH_HOME/common/dv/libs.cmd
|
||||
|
||||
declare -a core_arr=("dut_c2c")
|
||||
declare -a cfg_arr=("../hdl/cfg_c2c.v")
|
||||
|
||||
for core in "${core_arr[@]}"
|
||||
do
|
||||
for cfg in "${cfg_arr[@]}"
|
||||
do
|
||||
iverilog -g2005 -DTARGET_SIM=1 $cfg $core.v $DV -f $LIBS -o $core.bin
|
||||
done
|
||||
|
||||
done
|
||||
@ -1,13 +0,0 @@
|
||||
#!/bin/bash
|
||||
|
||||
#ARGUMENTS
|
||||
#$1=name of "dut*.bin" to simulate
|
||||
#$2=path to test to run
|
||||
|
||||
#Uses BASH $RANDOM variable to set seed
|
||||
|
||||
rm test_0.emf
|
||||
ln -s $2 test_0.emf
|
||||
./$1 +SEED=$RANDOM
|
||||
|
||||
|
||||
@ -1 +0,0 @@
|
||||
tests/test_random.emf
|
||||
@ -1,7 +0,0 @@
|
||||
#!/bin/bash
|
||||
top="../hdl/parallella_basic.v"
|
||||
iverilog -g2005 -DTARGET_SIM=1 -DTARGET_XILINX=1 $top -f ../../common/dv/libs.cmd -o ${dut}.vvp
|
||||
|
||||
#-pfileline=1
|
||||
#-Wall
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user