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Andreas Olofsson 2015-11-04 19:18:45 -05:00
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112
memory/ip/xilinx/doc/fifo_generator_v12_0_changelog.txt
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2015.2:
* Version 12.0 (Rev. 4)
* No changes
2015.1:
* Version 12.0 (Rev. 4)
* Delivering non encrypted behavioral models.
* Enabled out-of-context clock frequency setting by adding FREQ_HZ parameter to clock ports
* Enabling behavioral simulation for Built-in FIFO configurations changes the simulation file names and delivery structure.
* Supported devices and production status are now determined automatically, to simplify support for future devices
2014.4.1:
* Version 12.0 (Rev. 3)
* No changes
2014.4:
* Version 12.0 (Rev. 3)
* Reduced DRC warnings.
* Internal device family change, no functional changes
* Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
2014.3:
* Version 12.0 (Rev. 2)
* Added support for Asynchronous AXI Stream Packet FIFO for UltraScale devices.
* Added support for write data count and read data count for Asynchronous AXI Stream Packet FIFO for UltraScale devices.
* Added support for write data count and read data count for Common Clock Block RAM FIFO when Asymmetric Port Width option is enabled for UltraScale devices.
* Added support for Low Latency Built-in FIFO for UltraScale devices.
2014.2:
* Version 12.0 (Rev. 1)
* Repackaged to improve internal automation, no functional changes.
2014.1:
* Version 12.0
* Asynchronous reset port (rst) for Built-in FIFO configurations is removed for UltraScale Built-in FIFO configurations. When upgrading from previously released core, 'rst' port will be replaced by 'srst' port.
* Synchronous reset (srst) mechanism is changed now for UltraScale devices. FIFO Generator will now provide wr_rst_busy and rd_rst_busy output ports. When wr_rst_busy is active low, the core is ready for write operation and when rd_rst_busy is active low, the core is ready for read operation.
* Added asymmetric port width support for Common Clock Block RAM FIFO, Common Clock Built-in FIFO and Independent Clocks Built-in FIFO configurations for UltraScale Devices
* Added 'sleep' input port for Common Clock Built-in FIFO and Independent Clocks Built-in FIFO configurations only for UltraScale Devices
* Internal device family name change, no functional changes
2013.4:
* Version 11.0 (Rev. 1)
* Added support for Ultrascale devices
* Common Clock Builtin FIFO is set as default implementation type only for UltraScale devices
* Embedded Register option is always ON for Block RAM and Builtin FIFOs only for UltraScale devices
* Reset is sampled with respect to wr_clk/clk and then synchronized before the use in FIFO Generator only for UltraScale devices
2013.3:
* Version 11.0
* AXI ID Tags (s_axi_wid and m_axi_wid) are now determined by AXI protocol type (AXI4, AXI3). When upgrading from previously released core, these signals will be removed when AXI_Type = AXI4_Full.
* AXI Lock signals (s_axi_awlock, m_axi_awlock, s_axi_arlock and m_axi_arlock) are now determined by AXI Protocol type (AXI4, AXI3). When upgrading from previously released core, these signals width will reduce from 2-bits to 1-bit when AXI_Type=AXI4_Full
* Removed restriction on packet size in AXI4 Stream FIFO mode. Now, the packet size can be up to FIFO depth
* Enhanced support for IP Integrator
* Reduced warnings in synthesis and simulation
* Added support for Cadence IES and Synopsys VCS simulators
* Improved GUI speed and responsiveness, no functional changes
* Increased the maximum number of synchronization stages from 4 to 8. The minimum FIFO depth is limited to 32 when number of synchronization stages is > 4
2013.2:
* Version 10.0 (Rev. 1)
* Constraints processing order changed
2013.1:
* Version 10.0
* Native Vivado Release
* There have been no functional or interface changes to this IP. The version number has changed to support unique versioning in Vivado starting with 2013.1.
(c) Copyright 2002 - 2015 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
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related to, arising under or in connection with these
materials, including for any direct, or any indirect,
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(including loss of data, profits, goodwill, or any type of
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PART OF THIS FILE AT ALL TIMES.

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memory/ip/xilinx/fifo_async_104x32.upgrade_log
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Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2015.2 (lin64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
| Date : Wed Nov 4 17:11:52 2015
| Host : parallella running 64-bit Ubuntu 14.04.3 LTS
| Command : upgrade_ip
| Device : xc7z020clg400-1
------------------------------------------------------------------------------------
Upgrade Log for IP 'fifo_async_104x32'
1. Summary
----------
SUCCESS in the update of fifo_async_104x32 (xilinx.com:ip:fifo_generator:12.0 (Rev. 4)) to current project options.

32
memory/ip/xilinx/fifo_async_104x32_stub.v
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// Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2015.2 (lin64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
// Date : Wed Nov 4 19:05:28 2015
// Host : parallella running 64-bit Ubuntu 14.04.3 LTS
// Command : write_verilog -force -mode synth_stub
// /home/aolofsson/Work_all/oh/memory/ip/xilinx/fifo_async_104x32_stub.v
// Design : fifo_async_104x32
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg400-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "fifo_generator_v12_0,Vivado 2015.2" *)
module fifo_async_104x32(wr_clk, wr_rst, rd_clk, rd_rst, din, wr_en, rd_en, dout, full, almost_full, empty, valid, prog_full)
/* synthesis syn_black_box black_box_pad_pin="wr_clk,wr_rst,rd_clk,rd_rst,din[103:0],wr_en,rd_en,dout[103:0],full,almost_full,empty,valid,prog_full" */;
input wr_clk;
input wr_rst;
input rd_clk;
input rd_rst;
input [103:0]din;
input wr_en;
input rd_en;
output [103:0]dout;
output full;
output almost_full;
output empty;
output valid;
output prog_full;
endmodule

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memory/ip/xilinx/fifo_async_104x32_stub.vhdl
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-- Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2015.2 (lin64) Build 1266856 Fri Jun 26 16:35:25 MDT 2015
-- Date : Wed Nov 4 19:05:28 2015
-- Host : parallella running 64-bit Ubuntu 14.04.3 LTS
-- Command : write_vhdl -force -mode synth_stub
-- /home/aolofsson/Work_all/oh/memory/ip/xilinx/fifo_async_104x32_stub.vhdl
-- Design : fifo_async_104x32
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fifo_async_104x32 is
Port (
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 103 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 103 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
empty : out STD_LOGIC;
valid : out STD_LOGIC;
prog_full : out STD_LOGIC
);
end fifo_async_104x32;
architecture stub of fifo_async_104x32 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "wr_clk,wr_rst,rd_clk,rd_rst,din[103:0],wr_en,rd_en,dout[103:0],full,almost_full,empty,valid,prog_full";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "fifo_generator_v12_0,Vivado 2015.2";
begin
end;