diff --git a/common/hdl/clock_divider.v b/common/hdl/clock_divider.v
index 10a7329..5c7f956 100644
--- a/common/hdl/clock_divider.v
+++ b/common/hdl/clock_divider.v
@@ -40,18 +40,19 @@ module clock_divider(/*AUTOARG*/
 
    always @ (divcfg[3:0])
      casez (divcfg[3:0])
-	  4'b0010 : divcfg_dec[7:0] = 8'b00000010;  // Divide by 2
-	  4'b0011 : divcfg_dec[7:0] = 8'b00000100;  // Divide by 4
-	  4'b0100 : divcfg_dec[7:0] = 8'b00001000;  // Divide by 8
-	  4'b0101 : divcfg_dec[7:0] = 8'b00010000;  // Divide by 16
-	  4'b0110 : divcfg_dec[7:0] = 8'b00100000;  // Divide by 32
-          4'b0111 : divcfg_dec[7:0] = 8'b01000000;  // Divide by 64
+	  4'b0001 : divcfg_dec[7:0] = 8'b00000010;  // Divide by 2
+	  4'b0010 : divcfg_dec[7:0] = 8'b00000100;  // Divide by 4
+	  4'b0011 : divcfg_dec[7:0] = 8'b00001000;  // Divide by 8
+	  4'b0100 : divcfg_dec[7:0] = 8'b00010000;  // Divide by 16
+	  4'b0101 : divcfg_dec[7:0] = 8'b00100000;  // Divide by 32
+          4'b0110 : divcfg_dec[7:0] = 8'b01000000;  // Divide by 64
+          4'b0111 : divcfg_dec[7:0] = 8'b01000000;  // Divide by 128
 	  default : divcfg_dec[7:0] = 8'b0000000;   // others
 	endcase
    
    //Divide by two special case
-   assign div2_sel = divcfg[3:0]==4'b0010;
-   assign div1_sel = divcfg[3:0]==4'b0001;
+   assign div2_sel = divcfg[3:0]==4'b0001;
+   assign div1_sel = divcfg[3:0]==4'b0000;
     
    always @ (posedge clkin or posedge reset)
      if(reset)
diff --git a/elink/dv/dv_elink_tb.v b/elink/dv/dv_elink_tb.v
index 292027d..ae7f892 100644
--- a/elink/dv/dv_elink_tb.v
+++ b/elink/dv/dv_elink_tb.v
@@ -32,7 +32,7 @@ module dv_elink_tb();
 	  datamode = 2'b11;	
 	#400 
           //clock config (fast /2)
-          dv_elink.elink.ecfg.ecfg_clk_reg[15:0] = 16'h0011;
+          dv_elink.elink.ecfg.ecfg_clk_reg[15:0] = 16'h0113;
           //tx config  (enable)
    	  dv_elink.elink.ecfg.ecfg_tx_reg[8:0]   = 9'h001;
           //rx config (enable)