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Getting all the clk config numbers aligned

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Not changing these again!!
This commit is contained in:
Andreas Olofsson 2015-04-16 22:48:31 -04:00
parent 068d63279b
commit dca611c5ba
2 changed files with 10 additions and 9 deletions
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17
common/hdl/clock_divider.v
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@ -40,18 +40,19 @@ module clock_divider(/*AUTOARG*/
always @ (divcfg[3:0])
casez (divcfg[3:0])
4'b0010 : divcfg_dec[7:0] = 8'b00000010; // Divide by 2
4'b0011 : divcfg_dec[7:0] = 8'b00000100; // Divide by 4
4'b0100 : divcfg_dec[7:0] = 8'b00001000; // Divide by 8
4'b0101 : divcfg_dec[7:0] = 8'b00010000; // Divide by 16
4'b0110 : divcfg_dec[7:0] = 8'b00100000; // Divide by 32
4'b0111 : divcfg_dec[7:0] = 8'b01000000; // Divide by 64
4'b0001 : divcfg_dec[7:0] = 8'b00000010; // Divide by 2
4'b0010 : divcfg_dec[7:0] = 8'b00000100; // Divide by 4
4'b0011 : divcfg_dec[7:0] = 8'b00001000; // Divide by 8
4'b0100 : divcfg_dec[7:0] = 8'b00010000; // Divide by 16
4'b0101 : divcfg_dec[7:0] = 8'b00100000; // Divide by 32
4'b0110 : divcfg_dec[7:0] = 8'b01000000; // Divide by 64
4'b0111 : divcfg_dec[7:0] = 8'b01000000; // Divide by 128
default : divcfg_dec[7:0] = 8'b0000000; // others
endcase
//Divide by two special case
assign div2_sel = divcfg[3:0]==4'b0010;
assign div1_sel = divcfg[3:0]==4'b0001;
assign div2_sel = divcfg[3:0]==4'b0001;
assign div1_sel = divcfg[3:0]==4'b0000;
always @ (posedge clkin or posedge reset)
if(reset)

2
elink/dv/dv_elink_tb.v
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@ -32,7 +32,7 @@ module dv_elink_tb();
datamode = 2'b11;
#400
//clock config (fast /2)
dv_elink.elink.ecfg.ecfg_clk_reg[15:0] = 16'h0011;
dv_elink.elink.ecfg.ecfg_clk_reg[15:0] = 16'h0113;
//tx config (enable)
dv_elink.elink.ecfg.ecfg_tx_reg[8:0] = 9'h001;
//rx config (enable)