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Fixing unconnected wire bug

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This commit is contained in:
Andreas Olofsson 2015-12-05 09:01:18 -05:00
parent 2d953d5639
commit dd811ab417
2 changed files with 5 additions and 6 deletions
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2
common/hdl/oh_lat0.v
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@ -30,7 +30,7 @@ module oh_lat0 (/*AUTOARG*/
/* verilator lint_off COMBDLY */ /* verilator lint_off COMBDLY */
// # Real lat0 // # Real lat0
always @ (/*AUTOSENSE*/clk or in_sl) always @ (clk or in_sl)
if (~clk) if (~clk)
out_real_sh[DW-1:0] <= in_sl[DW-1:0]; out_real_sh[DW-1:0] <= in_sl[DW-1:0];
/* verilator lint_on COMBDLY */ /* verilator lint_on COMBDLY */

9
common/hdl/oh_lat1.v
View File

@ -15,14 +15,13 @@ module oh_lat1 (/*AUTOARG*/
// Outputs // Outputs
out_sl, out_sl,
// Inputs // Inputs
in_sh, clk, lat_clk in_sh, clk
); );
parameter DW=99; parameter DW=99;
input [DW-1:0] in_sh; input [DW-1:0] in_sh;
input clk; input clk;
input lat_clk;
output [DW-1:0] out_sl; output [DW-1:0] out_sl;
// # lat_clk is created in the following way: // # lat_clk is created in the following way:
@ -34,9 +33,9 @@ module oh_lat1 (/*AUTOARG*/
/* verilator lint_off COMBDLY */ /* verilator lint_off COMBDLY */
// # Real lat1 // # Real lat1
always @ (/*AUTOSENSE*/in_sh or lat_clk) always @ (clk or in_sh)
if (lat_clk) if (clk)
out_real_sl[DW-1:0] <= in_sh[DW-1:0]; out_real_sl[DW-1:0] <= in_sh[DW-1:0];
/* verilator lint_on COMBDLY */ /* verilator lint_on COMBDLY */
`ifdef DV_FAKELAT `ifdef DV_FAKELAT