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Integrating emesh memory module

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-This will flush out the final read response path
This commit is contained in:
Andreas Olofsson 2015-04-20 23:07:13 -04:00
parent 6a6f953986
commit e033e233d0
6 changed files with 109 additions and 205 deletions
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104
elink/dv/dv_elink.v
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@ -124,6 +124,9 @@ module dv_elink(/*AUTOARG*/
wire elink_axi_wready; // From esaxi of esaxi.v
wire [7:0] elink_axi_wstrb; // From elink of elink.v
wire elink_axi_wvalid; // From elink of elink.v
wire emem_emrq_wait; // From emem of emesh_memory.v
wire esaxi_emrr_access; // From emem of emesh_memory.v
wire [DW-1:0] esaxi_emrr_data; // From emem of emesh_memory.v
wire frame_n; // From elink of elink.v
wire frame_p; // From elink of elink.v
wire lclk_n; // From elink of elink.v
@ -134,7 +137,7 @@ module dv_elink(/*AUTOARG*/
wire wr_wait_p; // From elink of elink.v
// End of automatics
wire [63:0] dv_axi_rdata; //restricted to 32 bits here
wire [31:0] dv_axi_rdata; //restricted to 32 bits here
wire emaxi_emrq_rd_en; // From emaxi of emaxi.v
wire emaxi_emwr_rd_en; // From emaxi of emaxi.v
wire emaxi_emrq_access; // To emaxi of emaxi.v
@ -186,9 +189,10 @@ module dv_elink(/*AUTOARG*/
wire [1:0] dut_datamode; // To dut_monitor of emesh_monitor.v
wire [AW-1:0] dut_dstaddr; // To dut_monitor of emesh_monitor.v
wire [AW-1:0] dut_srcaddr; // To dut_monitor of emesh_monitor.v
wire dut_write; // To dut_monitor of emesh_monitor.v
wire dut_write; // To dut_monitor of emesh_monitor.v
wire emem_wait; // To emem of emesh_memory.v
//Clocks
wire clkin = clk[0]; //for pll-->cclk, rxclk, txclk
wire m_axi_aclk = clk[1];
@ -255,10 +259,10 @@ module dv_elink(/*AUTOARG*/
/*emaxi AUTO_TEMPLATE (
// Outputs
.m_\(.*\) (dv_\1[]),
.em\(.*\) (emaxi_em\1[]),
);
.m_\(.*\) (dv_\1[]),
.em\(.*\) (emaxi_em\1[]),
.m_axi_rdata ({dv_axi_rdata[31:0],dv_axi_rdata[31:0]}),
);
*/
//Drive the elink slave AXI interface
@ -325,7 +329,7 @@ module dv_elink(/*AUTOARG*/
.m_axi_bvalid (dv_axi_bvalid), // Templated
.m_axi_arready (dv_axi_arready), // Templated
.m_axi_rid (dv_axi_rid[IDW-1:0]), // Templated
.m_axi_rdata (dv_axi_rdata[63:0]), // Templated
.m_axi_rdata ({dv_axi_rdata[31:0],dv_axi_rdata[31:0]}), // Templated
.m_axi_rresp (dv_axi_rresp[1:0]), // Templated
.m_axi_rlast (dv_axi_rlast), // Templated
.m_axi_rvalid (dv_axi_rvalid)); // Templated
@ -336,14 +340,13 @@ module dv_elink(/*AUTOARG*/
.s_\(.*\) (elink_\1[]),
.mi_\(.*\) (),
.em\(.*\) (esaxi_em\1[]),
.emrq_progfull (emem_emrq_wait),
);
*/
esaxi esaxi (.emwr_progfull (1'b0),
.emrq_progfull (1'b0),
.emrr_data (32'b0),//no read from other side
.emrr_access (1'b0),
.mi_ecfg_dout (32'b0),
.mi_tx_emmu_dout (32'b0),
.mi_rx_emmu_dout (32'b0),
@ -390,6 +393,9 @@ module dv_elink(/*AUTOARG*/
.s_axi_rvalid (elink_axi_rvalid), // Templated
.s_axi_wready (elink_axi_wready), // Templated
// Inputs
.emrq_progfull (emem_emrq_wait), // Templated
.emrr_data (esaxi_emrr_data[31:0]), // Templated
.emrr_access (esaxi_emrr_access), // Templated
.s_axi_arid (elink_axi_arid[IDW-1:0]), // Templated
.s_axi_araddr (elink_axi_araddr[31:0]), // Templated
.s_axi_arburst (elink_axi_arburst[1:0]), // Templated
@ -427,7 +433,7 @@ module dv_elink(/*AUTOARG*/
.txi_\(.*\) (\1[]),
.s_\(.*\) (dv_\1[]),
.m_\(.*\) (elink_\1[]),
.m_axi_rdata ({32'b0,elink_axi_rdata[31:0]}), //restricted to slave width
.m_axi_rdata ({elink_axi_rdata[31:0],elink_axi_rdata[31:0]}), //restricted to slave width
);
*/
@ -515,7 +521,7 @@ module dv_elink(/*AUTOARG*/
.m_axi_bvalid (elink_axi_bvalid), // Templated
.m_axi_arready (elink_axi_arready), // Templated
.m_axi_rid (elink_axi_rid[IDW-1:0]), // Templated
.m_axi_rdata ({32'b0,elink_axi_rdata[31:0]}), // Templated
.m_axi_rdata ({elink_axi_rdata[31:0],elink_axi_rdata[31:0]}), // Templated
.m_axi_rresp (elink_axi_rresp[1:0]), // Templated
.m_axi_rlast (elink_axi_rlast), // Templated
.m_axi_rvalid (elink_axi_rvalid), // Templated
@ -548,6 +554,76 @@ module dv_elink(/*AUTOARG*/
.s_axi_wvalid (dv_axi_wvalid)); // Templated
wire emem_access;
wire emem_write;
wire [1:0] emem_datamode;
wire [3:0] emem_ctrlmode;
wire [AW-1:0] emem_dstaddr;
wire [DW-1:0] emem_data;
wire [AW-1:0] emem_srcaddr;
assign emem_access = esaxi_emwr_access | esaxi_emrq_access;
assign emem_write = esaxi_emwr_access;
assign emem_datamode[1:0] = esaxi_emwr_access ? esaxi_emwr_datamode[1:0] :
esaxi_emrq_datamode[1:0];
assign emem_ctrlmode[3:0] = esaxi_emwr_access ? esaxi_emwr_ctrlmode[3:0] :
esaxi_emrq_ctrlmode[3:0];
assign emem_dstaddr[AW-1:0] = esaxi_emwr_access ? esaxi_emwr_dstaddr[AW-1:0] :
esaxi_emrq_dstaddr[AW-1:0];
assign emem_dstaddr[AW-1:0] = esaxi_emwr_access ? esaxi_emwr_dstaddr[AW-1:0] :
esaxi_emrq_dstaddr[AW-1:0];
assign emem_dstaddr[AW-1:0] = esaxi_emwr_access ? esaxi_emwr_dstaddr[AW-1:0] :
esaxi_emrq_dstaddr[AW-1:0];
assign emem_data[DW-1:0] = esaxi_emwr_access ? esaxi_emwr_data[DW-1:0] :
esaxi_emrq_data[DW-1:0];
assign emem_srcaddr[AW-1:0] = esaxi_emwr_access ? esaxi_emwr_srcaddr[AW-1:0] :
esaxi_emrq_srcaddr[AW-1:0];
assign emem_wait = ~esaxi_emrr_rd_en & emem_access;
/*emesh_memory AUTO_TEMPLATE (
// Outputs
.\(.*\)_out (esaxi_emrr_\1[]),
.\(.*\)_in (emem_\1[]),
.wait_out (emem_emrq_wait),
);
*/
emesh_memory emem (.clk (s_axi_aclk),
.datamode_out (),
.ctrlmode_out (),
.dstaddr_out (),
.srcaddr_out (),
.write_out (),
// Inputs
/*AUTOINST*/
// Outputs
.wait_out (emem_emrq_wait), // Templated
.access_out (esaxi_emrr_access), // Templated
.data_out (esaxi_emrr_data[DW-1:0]), // Templated
// Inputs
.reset (reset),
.access_in (emem_access), // Templated
.write_in (emem_write), // Templated
.datamode_in (emem_datamode[1:0]), // Templated
.ctrlmode_in (emem_ctrlmode[3:0]), // Templated
.dstaddr_in (emem_dstaddr[AW-1:0]), // Templated
.data_in (emem_data[DW-1:0]), // Templated
.srcaddr_in (emem_srcaddr[AW-1:0]), // Templated
.wait_in (emem_wait)); // Templated
//Transaction Monitor
reg [31:0] etime;
always @ (posedge clkin or posedge reset)
@ -603,7 +679,7 @@ module dv_elink(/*AUTOARG*/
endmodule // dv_elink
// Local Variables:
// verilog-library-directories:("." "../hdl")
// verilog-library-directories:("." "../hdl" "../../memory/hdl")
// End:
/*

18
elink/hdl/emaxi.v
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@ -145,8 +145,8 @@ module emaxi(/*autoarg*/
wire readinfo_wren;
wire readinfo_rden;
wire readinfo_full;
wire [40:0] readinfo_out;
wire [40:0] readinfo_in;
wire [47:0] readinfo_out;
wire [47:0] readinfo_in;
//i/o connections. write address (aw)
assign m_axi_awburst[1:0] = 2'b01;
@ -309,29 +309,32 @@ module emaxi(/*autoarg*/
// read data comes back.
//----------------------------
assign readinfo_in[40:0] =
//TODO: Can we improve this??
assign readinfo_in[47:0] =
{
7'b0,
emrq_srcaddr[31:0],//40:9
emrq_dstaddr[2:0], //8:6
emrq_ctrlmode[3:0], //5:2
emrq_datamode[1:0]
};
fifo_sync
fifo_sync
#(
// parameters
.AW (5),
.DW (41))
.DW (48))
fifo_readinfo_i
(
// outputs
.rd_data (readinfo_out[40:0]),
.rd_data (readinfo_out[47:0]),
.rd_empty (),
.wr_full (readinfo_full),
// inputs
.clk (m_axi_aclk),
.reset (~m_axi_aresetn),
.wr_data (readinfo_in[40:0]),
.wr_data (readinfo_in[47:0]),
.wr_en (emrq_rd_en),
.rd_en (readinfo_rden));
@ -371,6 +374,7 @@ module emaxi(/*autoarg*/
emrr_srcaddr[31:0] <= m_axi_rdata[63:32];
// steer read data according to size & host address lsbs
//all data needs to be right aligned
//(this is due to the Epiphany right aligning all words)
case(readinfo_out[1:0])//datamode
2'd0: // byte read
case(readinfo_out[8:6])

6
elink/hdl/esaxi.v
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@ -494,7 +494,9 @@ module esaxi (/*autoarg*/
emrq_dstaddr[31:0] <= axi_araddr[31:0];
emrq_srcaddr[31:0] <= {c_read_tag_addr[11:0], 20'd0};//TODO? What can we do with lower 32 bits?
end
///Only letting through proper read requests
assign emrq_access=emrq_access_all & ~(emrq_dstaddr[31:20]==elinkid[11:0]);
//Read response AXI state machine
always @( posedge s_axi_aclk )
@ -519,8 +521,6 @@ module esaxi (/*autoarg*/
else if( s_axi_rready )
s_axi_rvalid <= 1'b0;
end // else: !if( s_axi_aresetn == 1'b0 )
assign emrq_access=emrq_access_all & ~(emrq_dstaddr[31:20]==elinkid[11:0]);
//###################################################
//#Register Inteface Logic

177
embox/hdl/axi_embox.v
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@ -1,177 +0,0 @@
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Andreas Olofsson <andreas@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
/*###########################################################################
# Function: AXI slave wrapper for mailbox FIFO
#
############################################################################
*/
module axi_embox (/*AUTOARG*/
// Outputs
s_axi_awready, s_axi_wready, s_axi_bresp, s_axi_bvalid,
s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid,
embox_full, embox_empty,
// Inputs
s_axi_aclk, s_axi_aresetn, s_axi_awaddr, s_axi_awlen, s_axi_awsize,
s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
s_axi_awvalid, s_axi_wdata, s_axi_wstrb, s_axi_wlast, s_axi_wvalid,
s_axi_bready, s_axi_araddr, s_axi_arlen, s_axi_arsize,
s_axi_arburst, s_axi_arlock, s_axi_arcache, s_axi_arprot,
s_axi_arvalid, s_axi_rready
);
parameter AW = 32; //axi addr width
parameter DW = 32; //axi data width
parameter SW = 4; //==ADW/8
parameter MAW = 6; //memory side address width
/*****************************/
/*AXI SLAVE INTERFACE */
/*****************************/
//Global signals
input s_axi_aclk; //clock source for axi slave interfaces
input s_axi_aresetn; //asynchronous reset signal, active low
//Write address channel
input [AW-1:0] s_axi_awaddr; //write address
input [3:0] s_axi_awlen; //burst length (number of data transfers)
input [2:0] s_axi_awsize; //burst size (size of each transfer)
input [1:0] s_axi_awburst; //burst type
input [1:0] s_axi_awlock; //lock type (atomic characteristics)
input [3:0] s_axi_awcache; //memory type
input [2:0] s_axi_awprot; //protection type
input s_axi_awvalid; //write address valid
output s_axi_awready; //write address ready
//Write data channel
input [DW-1:0] s_axi_wdata; //write data
input [SW-1:0] s_axi_wstrb; //write strobes
input s_axi_wlast; //indicats last write transfer in burst
input s_axi_wvalid; //write valid
output s_axi_wready; //write channel ready
//Buffered write response channel
input s_axi_bready; //write ready
output [1:0] s_axi_bresp; //write response
output s_axi_bvalid; //write response valid
//Read address channel
input [AW-1:0] s_axi_araddr; //read address
input [3:0] s_axi_arlen; //burst lenght (number of data transfers)
input [2:0] s_axi_arsize; //burst size (size of each transfer)
input [1:0] s_axi_arburst; //burst type
input [1:0] s_axi_arlock; //lock type (atomic characteristics)
input [3:0] s_axi_arcache; //memory type
input [2:0] s_axi_arprot; //protection type
input s_axi_arvalid; //read address valid
output s_axi_arready; //read address ready
//Read data channel
output [DW-1:0] s_axi_rdata; //read data
output [1:0] s_axi_rresp; //read response
output s_axi_rlast; //indicates last read transfer in burst
output s_axi_rvalid; //read valid
input s_axi_rready; //read ready
/*****************************/
/*MAILBOX OUTPUTS */
/*****************************/
output embox_full;
output embox_empty;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire mi_access; // From axi_memif of axi_memif.v
wire [MAW-1:0] mi_addr; // From axi_memif of axi_memif.v
wire [DW-1:0] mi_data_in; // From axi_memif of axi_memif.v
wire mi_write; // From axi_memif of axi_memif.v
// End of automatics
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [DW-1:0] mi_data_out; // From embox of embox.v
/*****************************/
/*AXI INSTANCE */
/*****************************/
axi_memif axi_memif(/*AUTOINST*/
// Outputs
.s_axi_awready (s_axi_awready),
.s_axi_wready (s_axi_wready),
.s_axi_bresp (s_axi_bresp[1:0]),
.s_axi_bvalid (s_axi_bvalid),
.s_axi_arready (s_axi_arready),
.s_axi_rdata (s_axi_rdata[DW-1:0]),
.s_axi_rresp (s_axi_rresp[1:0]),
.s_axi_rlast (s_axi_rlast),
.s_axi_rvalid (s_axi_rvalid),
.mi_addr (mi_addr[MAW-1:0]),
.mi_access (mi_access),
.mi_write (mi_write),
.mi_data_in (mi_data_in[DW-1:0]),
// Inputs
.s_axi_aclk (s_axi_aclk),
.s_axi_aresetn (s_axi_aresetn),
.s_axi_awaddr (s_axi_awaddr[AW-1:0]),
.s_axi_awlen (s_axi_awlen[3:0]),
.s_axi_awsize (s_axi_awsize[2:0]),
.s_axi_awburst (s_axi_awburst[1:0]),
.s_axi_awlock (s_axi_awlock[1:0]),
.s_axi_awcache (s_axi_awcache[3:0]),
.s_axi_awprot (s_axi_awprot[2:0]),
.s_axi_awvalid (s_axi_awvalid),
.s_axi_wdata (s_axi_wdata[DW-1:0]),
.s_axi_wstrb (s_axi_wstrb[SW-1:0]),
.s_axi_wlast (s_axi_wlast),
.s_axi_wvalid (s_axi_wvalid),
.s_axi_bready (s_axi_bready),
.s_axi_araddr (s_axi_araddr[AW-1:0]),
.s_axi_arlen (s_axi_arlen[3:0]),
.s_axi_arsize (s_axi_arsize[2:0]),
.s_axi_arburst (s_axi_arburst[1:0]),
.s_axi_arlock (s_axi_arlock[1:0]),
.s_axi_arcache (s_axi_arcache[3:0]),
.s_axi_arprot (s_axi_arprot[2:0]),
.s_axi_arvalid (s_axi_arvalid),
.s_axi_rready (s_axi_rready),
.mi_data_out (mi_data_out[DW-1:0]));
/*****************************/
/*EMBOX INSTANCE */
/*****************************/
embox embox (.mi_addr (mi_addr[5:0]),
/*AUTOINST*/
// Outputs
.mi_data_out (mi_data_out[DW-1:0]),
.embox_full (embox_full),
.embox_empty (embox_empty),
// Inputs
.reset (reset),
.clk (clk),
.mi_access (mi_access),
.mi_write (mi_write),
.mi_data_in (mi_data_in[DW-1:0]));
endmodule // emmu
// Local Variables:
// verilog-library-directories:("." "../axi")
// End:

5
memory/hdl/fifo_sync.v
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@ -87,6 +87,7 @@ module fifo_sync
);
end
endgenerate
`elsif TARGET_CLEAN
defparam mem.DW=DW;
@ -97,7 +98,7 @@ module fifo_sync
.rd_data (rd_data[DW-1:0]),
// Inputs
.wr_clk (clk),
.wr_en ({(DW/8){we_en}}),
.wr_en ({(DW/8){wr_en}}),
.wr_addr (wr_addr[AW-1:0]),
.wr_data (wr_data[DW-1:0]),
.rd_clk (clk),
@ -108,11 +109,11 @@ module fifo_sync
endmodule // fifo_sync
// Local Variables:
// verilog-library-directories:(".")
// End:
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Fred Huettig <fred@adapteva.com>

4
memory/hdl/memory_sp.v
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@ -13,11 +13,11 @@ module memory_sp(/*AUTOARG*/
parameter AW = 14;
parameter DW = 32;
parameter WED = DW/8; //one per byte
parameter WED = DW/8; //one write enable per byte
parameter MD = 1<<AW;//memory depth
//write-port
input clk; //write clock
input clk; //clock
input en; //memory access
input [WED-1:0] wen; //write enable vector
input [AW-1:0] addr;//address