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Integrating emesh memory module
-This will flush out the final read response path
This commit is contained in:
Andreas Olofsson
parent
6a6f953986
commit
e033e233d0
@ -124,6 +124,9 @@ module dv_elink(/*AUTOARG*/
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wire elink_axi_wready; // From esaxi of esaxi.v
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wire [7:0] elink_axi_wstrb; // From elink of elink.v
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wire elink_axi_wvalid; // From elink of elink.v
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wire emem_emrq_wait; // From emem of emesh_memory.v
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wire esaxi_emrr_access; // From emem of emesh_memory.v
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wire [DW-1:0] esaxi_emrr_data; // From emem of emesh_memory.v
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wire frame_n; // From elink of elink.v
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wire frame_p; // From elink of elink.v
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wire lclk_n; // From elink of elink.v
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@ -134,7 +137,7 @@ module dv_elink(/*AUTOARG*/
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wire wr_wait_p; // From elink of elink.v
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// End of automatics
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wire [63:0] dv_axi_rdata; //restricted to 32 bits here
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wire [31:0] dv_axi_rdata; //restricted to 32 bits here
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wire emaxi_emrq_rd_en; // From emaxi of emaxi.v
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wire emaxi_emwr_rd_en; // From emaxi of emaxi.v
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wire emaxi_emrq_access; // To emaxi of emaxi.v
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@ -187,6 +190,7 @@ module dv_elink(/*AUTOARG*/
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wire [AW-1:0] dut_dstaddr; // To dut_monitor of emesh_monitor.v
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wire [AW-1:0] dut_srcaddr; // To dut_monitor of emesh_monitor.v
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wire dut_write; // To dut_monitor of emesh_monitor.v
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wire emem_wait; // To emem of emesh_memory.v
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//Clocks
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@ -257,7 +261,7 @@ module dv_elink(/*AUTOARG*/
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// Outputs
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.m_\(.*\) (dv_\1[]),
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.em\(.*\) (emaxi_em\1[]),
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.m_axi_rdata ({dv_axi_rdata[31:0],dv_axi_rdata[31:0]}),
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);
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*/
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@ -325,7 +329,7 @@ module dv_elink(/*AUTOARG*/
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.m_axi_bvalid (dv_axi_bvalid), // Templated
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.m_axi_arready (dv_axi_arready), // Templated
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.m_axi_rid (dv_axi_rid[IDW-1:0]), // Templated
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.m_axi_rdata (dv_axi_rdata[63:0]), // Templated
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.m_axi_rdata ({dv_axi_rdata[31:0],dv_axi_rdata[31:0]}), // Templated
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.m_axi_rresp (dv_axi_rresp[1:0]), // Templated
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.m_axi_rlast (dv_axi_rlast), // Templated
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.m_axi_rvalid (dv_axi_rvalid)); // Templated
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@ -336,14 +340,13 @@ module dv_elink(/*AUTOARG*/
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.s_\(.*\) (elink_\1[]),
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.mi_\(.*\) (),
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.em\(.*\) (esaxi_em\1[]),
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.emrq_progfull (emem_emrq_wait),
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);
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*/
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esaxi esaxi (.emwr_progfull (1'b0),
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.emrq_progfull (1'b0),
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.emrr_data (32'b0),//no read from other side
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.emrr_access (1'b0),
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.mi_ecfg_dout (32'b0),
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.mi_tx_emmu_dout (32'b0),
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.mi_rx_emmu_dout (32'b0),
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@ -390,6 +393,9 @@ module dv_elink(/*AUTOARG*/
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.s_axi_rvalid (elink_axi_rvalid), // Templated
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.s_axi_wready (elink_axi_wready), // Templated
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// Inputs
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.emrq_progfull (emem_emrq_wait), // Templated
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.emrr_data (esaxi_emrr_data[31:0]), // Templated
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.emrr_access (esaxi_emrr_access), // Templated
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.s_axi_arid (elink_axi_arid[IDW-1:0]), // Templated
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.s_axi_araddr (elink_axi_araddr[31:0]), // Templated
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.s_axi_arburst (elink_axi_arburst[1:0]), // Templated
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@ -427,7 +433,7 @@ module dv_elink(/*AUTOARG*/
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.txi_\(.*\) (\1[]),
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.s_\(.*\) (dv_\1[]),
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.m_\(.*\) (elink_\1[]),
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.m_axi_rdata ({32'b0,elink_axi_rdata[31:0]}), //restricted to slave width
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.m_axi_rdata ({elink_axi_rdata[31:0],elink_axi_rdata[31:0]}), //restricted to slave width
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);
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*/
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@ -515,7 +521,7 @@ module dv_elink(/*AUTOARG*/
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.m_axi_bvalid (elink_axi_bvalid), // Templated
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.m_axi_arready (elink_axi_arready), // Templated
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.m_axi_rid (elink_axi_rid[IDW-1:0]), // Templated
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.m_axi_rdata ({32'b0,elink_axi_rdata[31:0]}), // Templated
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.m_axi_rdata ({elink_axi_rdata[31:0],elink_axi_rdata[31:0]}), // Templated
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.m_axi_rresp (elink_axi_rresp[1:0]), // Templated
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.m_axi_rlast (elink_axi_rlast), // Templated
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.m_axi_rvalid (elink_axi_rvalid), // Templated
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@ -548,6 +554,76 @@ module dv_elink(/*AUTOARG*/
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.s_axi_wvalid (dv_axi_wvalid)); // Templated
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wire emem_access;
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wire emem_write;
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wire [1:0] emem_datamode;
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wire [3:0] emem_ctrlmode;
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wire [AW-1:0] emem_dstaddr;
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wire [DW-1:0] emem_data;
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wire [AW-1:0] emem_srcaddr;
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assign emem_access = esaxi_emwr_access | esaxi_emrq_access;
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assign emem_write = esaxi_emwr_access;
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assign emem_datamode[1:0] = esaxi_emwr_access ? esaxi_emwr_datamode[1:0] :
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esaxi_emrq_datamode[1:0];
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assign emem_ctrlmode[3:0] = esaxi_emwr_access ? esaxi_emwr_ctrlmode[3:0] :
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esaxi_emrq_ctrlmode[3:0];
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assign emem_dstaddr[AW-1:0] = esaxi_emwr_access ? esaxi_emwr_dstaddr[AW-1:0] :
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esaxi_emrq_dstaddr[AW-1:0];
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assign emem_dstaddr[AW-1:0] = esaxi_emwr_access ? esaxi_emwr_dstaddr[AW-1:0] :
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esaxi_emrq_dstaddr[AW-1:0];
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assign emem_dstaddr[AW-1:0] = esaxi_emwr_access ? esaxi_emwr_dstaddr[AW-1:0] :
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esaxi_emrq_dstaddr[AW-1:0];
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assign emem_data[DW-1:0] = esaxi_emwr_access ? esaxi_emwr_data[DW-1:0] :
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esaxi_emrq_data[DW-1:0];
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assign emem_srcaddr[AW-1:0] = esaxi_emwr_access ? esaxi_emwr_srcaddr[AW-1:0] :
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esaxi_emrq_srcaddr[AW-1:0];
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assign emem_wait = ~esaxi_emrr_rd_en & emem_access;
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/*emesh_memory AUTO_TEMPLATE (
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// Outputs
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.\(.*\)_out (esaxi_emrr_\1[]),
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.\(.*\)_in (emem_\1[]),
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.wait_out (emem_emrq_wait),
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);
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*/
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emesh_memory emem (.clk (s_axi_aclk),
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.datamode_out (),
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.ctrlmode_out (),
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.dstaddr_out (),
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.srcaddr_out (),
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.write_out (),
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// Inputs
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/*AUTOINST*/
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// Outputs
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.wait_out (emem_emrq_wait), // Templated
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.access_out (esaxi_emrr_access), // Templated
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.data_out (esaxi_emrr_data[DW-1:0]), // Templated
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// Inputs
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.reset (reset),
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.access_in (emem_access), // Templated
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.write_in (emem_write), // Templated
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.datamode_in (emem_datamode[1:0]), // Templated
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.ctrlmode_in (emem_ctrlmode[3:0]), // Templated
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.dstaddr_in (emem_dstaddr[AW-1:0]), // Templated
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.data_in (emem_data[DW-1:0]), // Templated
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.srcaddr_in (emem_srcaddr[AW-1:0]), // Templated
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.wait_in (emem_wait)); // Templated
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//Transaction Monitor
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reg [31:0] etime;
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always @ (posedge clkin or posedge reset)
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@ -603,7 +679,7 @@ module dv_elink(/*AUTOARG*/
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endmodule // dv_elink
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// Local Variables:
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// verilog-library-directories:("." "../hdl")
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// verilog-library-directories:("." "../hdl" "../../memory/hdl")
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// End:
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/*
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@ -145,8 +145,8 @@ module emaxi(/*autoarg*/
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wire readinfo_wren;
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wire readinfo_rden;
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wire readinfo_full;
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wire [40:0] readinfo_out;
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wire [40:0] readinfo_in;
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wire [47:0] readinfo_out;
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wire [47:0] readinfo_in;
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//i/o connections. write address (aw)
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assign m_axi_awburst[1:0] = 2'b01;
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@ -309,8 +309,11 @@ module emaxi(/*autoarg*/
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// read data comes back.
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//----------------------------
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assign readinfo_in[40:0] =
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//TODO: Can we improve this??
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assign readinfo_in[47:0] =
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{
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7'b0,
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emrq_srcaddr[31:0],//40:9
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emrq_dstaddr[2:0], //8:6
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emrq_ctrlmode[3:0], //5:2
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@ -321,17 +324,17 @@ module emaxi(/*autoarg*/
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#(
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// parameters
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.AW (5),
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.DW (41))
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.DW (48))
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fifo_readinfo_i
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(
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// outputs
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.rd_data (readinfo_out[40:0]),
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.rd_data (readinfo_out[47:0]),
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.rd_empty (),
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.wr_full (readinfo_full),
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// inputs
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.clk (m_axi_aclk),
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.reset (~m_axi_aresetn),
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.wr_data (readinfo_in[40:0]),
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.wr_data (readinfo_in[47:0]),
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.wr_en (emrq_rd_en),
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.rd_en (readinfo_rden));
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@ -371,6 +374,7 @@ module emaxi(/*autoarg*/
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emrr_srcaddr[31:0] <= m_axi_rdata[63:32];
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// steer read data according to size & host address lsbs
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//all data needs to be right aligned
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//(this is due to the Epiphany right aligning all words)
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case(readinfo_out[1:0])//datamode
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2'd0: // byte read
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case(readinfo_out[8:6])
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@ -495,6 +495,8 @@ module esaxi (/*autoarg*/
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emrq_srcaddr[31:0] <= {c_read_tag_addr[11:0], 20'd0};//TODO? What can we do with lower 32 bits?
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end
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///Only letting through proper read requests
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assign emrq_access=emrq_access_all & ~(emrq_dstaddr[31:20]==elinkid[11:0]);
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//Read response AXI state machine
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always @( posedge s_axi_aclk )
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@ -520,8 +522,6 @@ module esaxi (/*autoarg*/
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s_axi_rvalid <= 1'b0;
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end // else: !if( s_axi_aresetn == 1'b0 )
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assign emrq_access=emrq_access_all & ~(emrq_dstaddr[31:20]==elinkid[11:0]);
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//###################################################
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//#Register Inteface Logic
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//###################################################
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@ -1,177 +0,0 @@
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/*
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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/*###########################################################################
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# Function: AXI slave wrapper for mailbox FIFO
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#
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############################################################################
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*/
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module axi_embox (/*AUTOARG*/
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// Outputs
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s_axi_awready, s_axi_wready, s_axi_bresp, s_axi_bvalid,
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s_axi_arready, s_axi_rdata, s_axi_rresp, s_axi_rlast, s_axi_rvalid,
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embox_full, embox_empty,
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// Inputs
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s_axi_aclk, s_axi_aresetn, s_axi_awaddr, s_axi_awlen, s_axi_awsize,
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s_axi_awburst, s_axi_awlock, s_axi_awcache, s_axi_awprot,
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s_axi_awvalid, s_axi_wdata, s_axi_wstrb, s_axi_wlast, s_axi_wvalid,
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s_axi_bready, s_axi_araddr, s_axi_arlen, s_axi_arsize,
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s_axi_arburst, s_axi_arlock, s_axi_arcache, s_axi_arprot,
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s_axi_arvalid, s_axi_rready
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);
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parameter AW = 32; //axi addr width
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parameter DW = 32; //axi data width
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parameter SW = 4; //==ADW/8
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parameter MAW = 6; //memory side address width
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/*****************************/
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/*AXI SLAVE INTERFACE */
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/*****************************/
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//Global signals
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input s_axi_aclk; //clock source for axi slave interfaces
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input s_axi_aresetn; //asynchronous reset signal, active low
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//Write address channel
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input [AW-1:0] s_axi_awaddr; //write address
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input [3:0] s_axi_awlen; //burst length (number of data transfers)
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input [2:0] s_axi_awsize; //burst size (size of each transfer)
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input [1:0] s_axi_awburst; //burst type
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input [1:0] s_axi_awlock; //lock type (atomic characteristics)
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input [3:0] s_axi_awcache; //memory type
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input [2:0] s_axi_awprot; //protection type
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input s_axi_awvalid; //write address valid
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output s_axi_awready; //write address ready
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//Write data channel
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input [DW-1:0] s_axi_wdata; //write data
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input [SW-1:0] s_axi_wstrb; //write strobes
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input s_axi_wlast; //indicats last write transfer in burst
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input s_axi_wvalid; //write valid
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output s_axi_wready; //write channel ready
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//Buffered write response channel
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input s_axi_bready; //write ready
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output [1:0] s_axi_bresp; //write response
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output s_axi_bvalid; //write response valid
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//Read address channel
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input [AW-1:0] s_axi_araddr; //read address
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input [3:0] s_axi_arlen; //burst lenght (number of data transfers)
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input [2:0] s_axi_arsize; //burst size (size of each transfer)
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input [1:0] s_axi_arburst; //burst type
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input [1:0] s_axi_arlock; //lock type (atomic characteristics)
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input [3:0] s_axi_arcache; //memory type
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input [2:0] s_axi_arprot; //protection type
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input s_axi_arvalid; //read address valid
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output s_axi_arready; //read address ready
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//Read data channel
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output [DW-1:0] s_axi_rdata; //read data
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output [1:0] s_axi_rresp; //read response
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output s_axi_rlast; //indicates last read transfer in burst
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output s_axi_rvalid; //read valid
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input s_axi_rready; //read ready
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/*****************************/
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/*MAILBOX OUTPUTS */
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/*****************************/
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output embox_full;
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output embox_empty;
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire mi_access; // From axi_memif of axi_memif.v
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wire [MAW-1:0] mi_addr; // From axi_memif of axi_memif.v
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wire [DW-1:0] mi_data_in; // From axi_memif of axi_memif.v
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wire mi_write; // From axi_memif of axi_memif.v
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// End of automatics
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [DW-1:0] mi_data_out; // From embox of embox.v
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/*****************************/
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/*AXI INSTANCE */
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/*****************************/
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axi_memif axi_memif(/*AUTOINST*/
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// Outputs
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.s_axi_awready (s_axi_awready),
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.s_axi_wready (s_axi_wready),
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.s_axi_bresp (s_axi_bresp[1:0]),
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.s_axi_bvalid (s_axi_bvalid),
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.s_axi_arready (s_axi_arready),
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.s_axi_rdata (s_axi_rdata[DW-1:0]),
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.s_axi_rresp (s_axi_rresp[1:0]),
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.s_axi_rlast (s_axi_rlast),
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.s_axi_rvalid (s_axi_rvalid),
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.mi_addr (mi_addr[MAW-1:0]),
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.mi_access (mi_access),
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.mi_write (mi_write),
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.mi_data_in (mi_data_in[DW-1:0]),
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// Inputs
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.s_axi_aclk (s_axi_aclk),
|
||||
.s_axi_aresetn (s_axi_aresetn),
|
||||
.s_axi_awaddr (s_axi_awaddr[AW-1:0]),
|
||||
.s_axi_awlen (s_axi_awlen[3:0]),
|
||||
.s_axi_awsize (s_axi_awsize[2:0]),
|
||||
.s_axi_awburst (s_axi_awburst[1:0]),
|
||||
.s_axi_awlock (s_axi_awlock[1:0]),
|
||||
.s_axi_awcache (s_axi_awcache[3:0]),
|
||||
.s_axi_awprot (s_axi_awprot[2:0]),
|
||||
.s_axi_awvalid (s_axi_awvalid),
|
||||
.s_axi_wdata (s_axi_wdata[DW-1:0]),
|
||||
.s_axi_wstrb (s_axi_wstrb[SW-1:0]),
|
||||
.s_axi_wlast (s_axi_wlast),
|
||||
.s_axi_wvalid (s_axi_wvalid),
|
||||
.s_axi_bready (s_axi_bready),
|
||||
.s_axi_araddr (s_axi_araddr[AW-1:0]),
|
||||
.s_axi_arlen (s_axi_arlen[3:0]),
|
||||
.s_axi_arsize (s_axi_arsize[2:0]),
|
||||
.s_axi_arburst (s_axi_arburst[1:0]),
|
||||
.s_axi_arlock (s_axi_arlock[1:0]),
|
||||
.s_axi_arcache (s_axi_arcache[3:0]),
|
||||
.s_axi_arprot (s_axi_arprot[2:0]),
|
||||
.s_axi_arvalid (s_axi_arvalid),
|
||||
.s_axi_rready (s_axi_rready),
|
||||
.mi_data_out (mi_data_out[DW-1:0]));
|
||||
|
||||
|
||||
/*****************************/
|
||||
/*EMBOX INSTANCE */
|
||||
/*****************************/
|
||||
embox embox (.mi_addr (mi_addr[5:0]),
|
||||
/*AUTOINST*/
|
||||
// Outputs
|
||||
.mi_data_out (mi_data_out[DW-1:0]),
|
||||
.embox_full (embox_full),
|
||||
.embox_empty (embox_empty),
|
||||
// Inputs
|
||||
.reset (reset),
|
||||
.clk (clk),
|
||||
.mi_access (mi_access),
|
||||
.mi_write (mi_write),
|
||||
.mi_data_in (mi_data_in[DW-1:0]));
|
||||
|
||||
|
||||
endmodule // emmu
|
||||
// Local Variables:
|
||||
// verilog-library-directories:("." "../axi")
|
||||
// End:
|
||||
|
||||
|
||||
|
||||
@ -87,6 +87,7 @@ module fifo_sync
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
`elsif TARGET_CLEAN
|
||||
|
||||
defparam mem.DW=DW;
|
||||
@ -97,7 +98,7 @@ module fifo_sync
|
||||
.rd_data (rd_data[DW-1:0]),
|
||||
// Inputs
|
||||
.wr_clk (clk),
|
||||
.wr_en ({(DW/8){we_en}}),
|
||||
.wr_en ({(DW/8){wr_en}}),
|
||||
.wr_addr (wr_addr[AW-1:0]),
|
||||
.wr_data (wr_data[DW-1:0]),
|
||||
.rd_clk (clk),
|
||||
@ -108,11 +109,11 @@ module fifo_sync
|
||||
|
||||
|
||||
endmodule // fifo_sync
|
||||
|
||||
// Local Variables:
|
||||
// verilog-library-directories:(".")
|
||||
// End:
|
||||
|
||||
|
||||
/*
|
||||
Copyright (C) 2014 Adapteva, Inc.
|
||||
Contributed by Fred Huettig <fred@adapteva.com>
|
||||
|
||||
@ -13,11 +13,11 @@ module memory_sp(/*AUTOARG*/
|
||||
|
||||
parameter AW = 14;
|
||||
parameter DW = 32;
|
||||
parameter WED = DW/8; //one per byte
|
||||
parameter WED = DW/8; //one write enable per byte
|
||||
parameter MD = 1<<AW;//memory depth
|
||||
|
||||
//write-port
|
||||
input clk; //write clock
|
||||
input clk; //clock
|
||||
input en; //memory access
|
||||
input [WED-1:0] wen; //write enable vector
|
||||
input [AW-1:0] addr;//address
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user