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Adding 2nd elink to dv env
-The single link env wasn't giving enough coverage -This is also preparing for inserting the chip reference model...
This commit is contained in:
Andreas Olofsson
parent
6b108f5e1f
commit
e1a295998f
@ -32,24 +32,66 @@ module dv_elink(/*AUTOARG*/
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input ext_wr_wait;
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/*AUTOINPUT*/
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/*AUTOOUTPUT*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [7:0] data_n; // From elink of elink.v
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wire [7:0] data_p; // From elink of elink.v
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wire frame_n; // From elink of elink.v
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wire frame_p; // From elink of elink.v
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wire lclk_n; // From elink of elink.v
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wire lclk_p; // From elink of elink.v
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wire rd_wait_n; // From elink of elink.v
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wire rd_wait_p; // From elink of elink.v
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wire wr_wait_n; // From elink of elink.v
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wire wr_wait_p; // From elink of elink.v
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wire elink0_cclk_n; // From elink0 of elink.v
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wire elink0_cclk_p; // From elink0 of elink.v
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wire elink0_chip_resetb; // From elink0 of elink.v
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wire [3:0] elink0_colid; // From elink0 of elink.v
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wire elink0_mailbox_full; // From elink0 of elink.v
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wire elink0_mailbox_not_empty;// From elink0 of elink.v
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wire [3:0] elink0_rowid; // From elink0 of elink.v
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wire elink0_rxo_rd_wait_n; // From elink0 of elink.v
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wire elink0_rxo_rd_wait_p; // From elink0 of elink.v
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wire elink0_rxo_wr_wait_n; // From elink0 of elink.v
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wire elink0_rxo_wr_wait_p; // From elink0 of elink.v
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wire elink0_rxrd_access; // From elink0 of elink.v
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wire [PW-1:0] elink0_rxrd_packet; // From elink0 of elink.v
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wire elink0_rxrr_access; // From elink0 of elink.v
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wire [PW-1:0] elink0_rxrr_packet; // From elink0 of elink.v
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wire elink0_rxwr_access; // From elink0 of elink.v
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wire [PW-1:0] elink0_rxwr_packet; // From elink0 of elink.v
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wire elink0_timeout; // From elink0 of elink.v
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wire [7:0] elink0_txo_data_n; // From elink0 of elink.v
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wire [7:0] elink0_txo_data_p; // From elink0 of elink.v
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wire elink0_txo_frame_n; // From elink0 of elink.v
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wire elink0_txo_frame_p; // From elink0 of elink.v
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wire elink0_txo_lclk_n; // From elink0 of elink.v
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wire elink0_txo_lclk_p; // From elink0 of elink.v
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wire elink0_txrd_wait; // From elink0 of elink.v
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wire elink0_txrr_wait; // From elink0 of elink.v
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wire elink0_txwr_wait; // From elink0 of elink.v
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wire elink1_cclk_n; // From elink1 of elink.v
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wire elink1_cclk_p; // From elink1 of elink.v
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wire elink1_chip_resetb; // From elink1 of elink.v
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wire [3:0] elink1_colid; // From elink1 of elink.v
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wire elink1_mailbox_full; // From elink1 of elink.v
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wire elink1_mailbox_not_empty;// From elink1 of elink.v
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wire [3:0] elink1_rowid; // From elink1 of elink.v
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wire elink1_rxo_rd_wait_n; // From elink1 of elink.v
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wire elink1_rxo_rd_wait_p; // From elink1 of elink.v
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wire elink1_rxo_wr_wait_n; // From elink1 of elink.v
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wire elink1_rxo_wr_wait_p; // From elink1 of elink.v
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wire elink1_rxrd_access; // From elink1 of elink.v
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wire [PW-1:0] elink1_rxrd_packet; // From elink1 of elink.v
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wire elink1_rxrr_access; // From elink1 of elink.v
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wire [PW-1:0] elink1_rxrr_packet; // From elink1 of elink.v
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wire elink1_rxwr_access; // From elink1 of elink.v
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wire [PW-1:0] elink1_rxwr_packet; // From elink1 of elink.v
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wire elink1_timeout; // From elink1 of elink.v
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wire [7:0] elink1_txo_data_n; // From elink1 of elink.v
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wire [7:0] elink1_txo_data_p; // From elink1 of elink.v
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wire elink1_txo_frame_n; // From elink1 of elink.v
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wire elink1_txo_frame_p; // From elink1 of elink.v
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wire elink1_txo_lclk_n; // From elink1 of elink.v
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wire elink1_txo_lclk_p; // From elink1 of elink.v
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wire elink1_txrd_wait; // From elink1 of elink.v
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wire elink1_txrr_access; // From emem of ememory.v
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wire [PW-1:0] elink1_txrr_packet; // From emem of ememory.v
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wire elink1_txrr_wait; // From elink1 of elink.v
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wire elink1_txwr_wait; // From elink1 of elink.v
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// End of automatics
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wire [3:0] colid;
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wire [3:0] rowid;
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wire mailbox_full;
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@ -68,13 +110,17 @@ module dv_elink(/*AUTOARG*/
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wire rxrd_access;
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wire [PW-1:0] rxrd_packet;
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wire txrr_access;
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wire [PW-1:0] txrr_packet;
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wire txwr_access;
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wire [PW-1:0] txwr_packet;
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wire txrd_access;
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wire [PW-1:0] txrd_packet;
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wire elink0_txrr_access;
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wire [PW-1:0] elink0_txrr_packet;
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wire elink0_txwr_access;
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wire [PW-1:0] elink0_txwr_packet;
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wire elink0_txrd_access;
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wire [PW-1:0] elink0_txrd_packet;
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wire elink1_txwr_access;
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wire [PW-1:0] elink1_txwr_packet;
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wire elink1_txrd_access;
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wire [PW-1:0] elink1_txrd_packet;
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wire txrd_wait;
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wire txwr_wait;
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@ -90,108 +136,163 @@ module dv_elink(/*AUTOARG*/
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//Clocks
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wire clkin = clk[0]; //for pll-->cclk, rxclk, txclk
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//Splitting transaction into read/write path
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//Read path
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assign txrd_access = ext_access & ~ext_packet[1];
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assign txrd_packet[PW-1:0] = ext_packet[PW-1:0];
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assign elink0_txrd_access = ext_access & ~ext_packet[1];
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assign elink0_txrd_packet[PW-1:0] = ext_packet[PW-1:0];
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//Write path
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assign txwr_access = ext_access & ext_packet[1];
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assign txwr_packet[PW-1:0] = ext_packet[PW-1:0];
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assign elink0_txwr_access = ext_access & ext_packet[1];
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assign elink0_txwr_packet[PW-1:0] = ext_packet[PW-1:0];
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//TX Pushback
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assign dut_rd_wait = txrd_wait;
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assign dut_wr_wait = txwr_wait;
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assign dut_rd_wait = elink0_txrd_wait;
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assign dut_wr_wait = elink0_txwr_wait;
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//Getting results back
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assign dut_access = rxrr_access;
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assign dut_packet[PW-1:0] = rxrr_packet[PW-1:0];
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assign dut_access = elink0_rxrr_access;
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assign dut_packet[PW-1:0] = elink0_rxrr_packet[PW-1:0];
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/*elink AUTO_TEMPLATE (
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// Outputs
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.txo_\(.*\) (\1[]),
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.rxi_\(.*\) (\1[]),
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.rxo_\(.*\) (\1[]),
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.txi_\(.*\) (\1[]),
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.\(.*\)_clk (clk[1]),
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);
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*/
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//No pushback testing on elink0
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assign elink0_rxrd_wait = 1'b0;
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assign elink0_rxwr_wait = 1'b0;
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assign elink0_rxrr_wait = 1'b0;
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defparam elink.TXID = 12'h810;
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defparam elink.RXID = 12'h820;
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elink elink (.hard_reset (reset),
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.mailbox_not_empty (mailbox_not_empty),
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.mailbox_full (mailbox_full),
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.chip_resetb (chip_resetb),
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.colid (colid[3:0]),
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.rowid (rowid[3:0]),
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.cclk_p (cclk_p),
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.cclk_n (cclk_n),
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.clkin (clkin),
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.clkbypass ({clkin,clkin,clkin}),
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.rxrd_access (rxrd_access),//to emem
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.rxrd_packet (rxrd_packet[PW-1:0]),
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.rxwr_access (rxwr_access),//to emem
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.rxwr_packet (rxwr_packet[PW-1:0]),
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.rxrr_access (rxrr_access),//to ext
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.rxrr_packet (rxrr_packet[PW-1:0]),
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.txrd_access (txrd_access),//from ext
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.txrd_packet (txrd_packet[PW-1:0]),
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.txwr_access (txwr_access),//from ext
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.txwr_packet (txwr_packet[PW-1:0]),
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.txrd_wait (txrd_wait),
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.txrr_wait (txrr_wait),
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.txwr_wait (txwr_wait),
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.rxrr_wait (ext_wr_wait),
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.rxwr_wait (1'b0),
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.timeout (timeout),
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/*AUTOINST*/
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// Outputs
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.rxo_wr_wait_p (wr_wait_p), // Templated
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.rxo_wr_wait_n (wr_wait_n), // Templated
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.rxo_rd_wait_p (rd_wait_p), // Templated
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.rxo_rd_wait_n (rd_wait_n), // Templated
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.txo_lclk_p (lclk_p), // Templated
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.txo_lclk_n (lclk_n), // Templated
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.txo_frame_p (frame_p), // Templated
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.txo_frame_n (frame_n), // Templated
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.txo_data_p (data_p[7:0]), // Templated
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.txo_data_n (data_n[7:0]), // Templated
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// Inputs
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.rxi_lclk_p (lclk_p), // Templated
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.rxi_lclk_n (lclk_n), // Templated
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.rxi_frame_p (frame_p), // Templated
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.rxi_frame_n (frame_n), // Templated
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.rxi_data_p (data_p[7:0]), // Templated
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.rxi_data_n (data_n[7:0]), // Templated
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.txi_wr_wait_p (wr_wait_p), // Templated
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.txi_wr_wait_n (wr_wait_n), // Templated
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.txi_rd_wait_p (rd_wait_p), // Templated
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.txi_rd_wait_n (rd_wait_n), // Templated
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.rxwr_clk (clk[1]), // Templated
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.rxrd_clk (clk[1]), // Templated
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.rxrd_wait (rxrd_wait),
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.rxrr_clk (clk[1]), // Templated
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.txwr_clk (clk[1]), // Templated
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.txrd_clk (clk[1]), // Templated
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.txrr_clk (clk[1]), // Templated
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.txrr_access (txrr_access),
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.txrr_packet (txrr_packet[PW-1:0]));
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/*elink AUTO_TEMPLATE (
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// Outputs
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.hard_reset (reset),
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.clkbypass ({clkin,clkin,clkin}),
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.clkin (clkin),
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.sys_clk (clk[1]),
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.\(.*\) (@"(substring vl-cell-name 0 6)"_\1[]),
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);
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*/
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defparam elink0.ID = 12'h810;
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elink elink0 (.txrr_access (),//not used
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.txrr_packet (),//not used
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.rxi_lclk_p (elink1_txo_lclk_p),
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.rxi_lclk_n (elink1_txo_lclk_n),
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.rxi_frame_p (elink1_txo_frame_p),
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.rxi_frame_n (elink1_txo_frame_n),
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.rxi_data_p (elink1_txo_data_p[7:0]),
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.rxi_data_n (elink1_txo_data_n[7:0]),
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.txi_wr_wait_p (elink1_rxo_wr_wait_p),
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.txi_wr_wait_n (elink1_rxo_wr_wait_n),
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.txi_rd_wait_p (elink1_rxo_rd_wait_p),
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.txi_rd_wait_n (elink1_rxo_rd_wait_n),
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/*AUTOINST*/
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// Outputs
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.colid (elink0_colid[3:0]), // Templated
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.rowid (elink0_rowid[3:0]), // Templated
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.chip_resetb (elink0_chip_resetb), // Templated
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.cclk_p (elink0_cclk_p), // Templated
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.cclk_n (elink0_cclk_n), // Templated
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.rxo_wr_wait_p (elink0_rxo_wr_wait_p), // Templated
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.rxo_wr_wait_n (elink0_rxo_wr_wait_n), // Templated
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.rxo_rd_wait_p (elink0_rxo_rd_wait_p), // Templated
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.rxo_rd_wait_n (elink0_rxo_rd_wait_n), // Templated
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.txo_lclk_p (elink0_txo_lclk_p), // Templated
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.txo_lclk_n (elink0_txo_lclk_n), // Templated
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.txo_frame_p (elink0_txo_frame_p), // Templated
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.txo_frame_n (elink0_txo_frame_n), // Templated
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.txo_data_p (elink0_txo_data_p[7:0]), // Templated
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.txo_data_n (elink0_txo_data_n[7:0]), // Templated
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.mailbox_not_empty (elink0_mailbox_not_empty), // Templated
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.mailbox_full (elink0_mailbox_full), // Templated
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.timeout (elink0_timeout), // Templated
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.rxwr_access (elink0_rxwr_access), // Templated
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.rxwr_packet (elink0_rxwr_packet[PW-1:0]), // Templated
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.rxrd_access (elink0_rxrd_access), // Templated
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.rxrd_packet (elink0_rxrd_packet[PW-1:0]), // Templated
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.rxrr_access (elink0_rxrr_access), // Templated
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.rxrr_packet (elink0_rxrr_packet[PW-1:0]), // Templated
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.txwr_wait (elink0_txwr_wait), // Templated
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.txrd_wait (elink0_txrd_wait), // Templated
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.txrr_wait (elink0_txrr_wait), // Templated
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// Inputs
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.hard_reset (reset), // Templated
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.clkin (clkin), // Templated
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.clkbypass ({clkin,clkin,clkin}), // Templated
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.sys_clk (clk[1]), // Templated
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.rxwr_wait (elink0_rxwr_wait), // Templated
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.rxrd_wait (elink0_rxrd_wait), // Templated
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.rxrr_wait (elink0_rxrr_wait), // Templated
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.txwr_access (elink0_txwr_access), // Templated
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.txwr_packet (elink0_txwr_packet[PW-1:0]), // Templated
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.txrd_access (elink0_txrd_access), // Templated
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.txrd_packet (elink0_txrd_packet[PW-1:0])); // Templated
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assign emem_access = rxwr_access | rxrd_access;
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defparam elink1.ID = 12'h820;
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elink elink1 (.rxi_lclk_p (elink0_txo_lclk_p),
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.rxi_lclk_n (elink0_txo_lclk_n),
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.rxi_frame_p (elink0_txo_frame_p),
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.rxi_frame_n (elink0_txo_frame_n),
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.rxi_data_p (elink0_txo_data_p[7:0]),
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.rxi_data_n (elink0_txo_data_n[7:0]),
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.txi_wr_wait_p (elink0_rxo_wr_wait_p),
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.txi_wr_wait_n (elink0_rxo_wr_wait_n),
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.txi_rd_wait_p (elink0_rxo_rd_wait_p),
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.txi_rd_wait_n (elink0_rxo_rd_wait_n),
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/*AUTOINST*/
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// Outputs
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.colid (elink1_colid[3:0]), // Templated
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.rowid (elink1_rowid[3:0]), // Templated
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.chip_resetb (elink1_chip_resetb), // Templated
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.cclk_p (elink1_cclk_p), // Templated
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.cclk_n (elink1_cclk_n), // Templated
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.rxo_wr_wait_p (elink1_rxo_wr_wait_p), // Templated
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.rxo_wr_wait_n (elink1_rxo_wr_wait_n), // Templated
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.rxo_rd_wait_p (elink1_rxo_rd_wait_p), // Templated
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.rxo_rd_wait_n (elink1_rxo_rd_wait_n), // Templated
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.txo_lclk_p (elink1_txo_lclk_p), // Templated
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.txo_lclk_n (elink1_txo_lclk_n), // Templated
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.txo_frame_p (elink1_txo_frame_p), // Templated
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.txo_frame_n (elink1_txo_frame_n), // Templated
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.txo_data_p (elink1_txo_data_p[7:0]), // Templated
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.txo_data_n (elink1_txo_data_n[7:0]), // Templated
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.mailbox_not_empty (elink1_mailbox_not_empty), // Templated
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.mailbox_full (elink1_mailbox_full), // Templated
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.timeout (elink1_timeout), // Templated
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.rxwr_access (elink1_rxwr_access), // Templated
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.rxwr_packet (elink1_rxwr_packet[PW-1:0]), // Templated
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.rxrd_access (elink1_rxrd_access), // Templated
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.rxrd_packet (elink1_rxrd_packet[PW-1:0]), // Templated
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.rxrr_access (elink1_rxrr_access), // Templated
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.rxrr_packet (elink1_rxrr_packet[PW-1:0]), // Templated
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.txwr_wait (elink1_txwr_wait), // Templated
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.txrd_wait (elink1_txrd_wait), // Templated
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.txrr_wait (elink1_txrr_wait), // Templated
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// Inputs
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.hard_reset (reset), // Templated
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.clkin (clkin), // Templated
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.clkbypass ({clkin,clkin,clkin}), // Templated
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.sys_clk (clk[1]), // Templated
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.rxwr_wait (elink1_rxwr_wait), // Templated
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.rxrd_wait (elink1_rxrd_wait), // Templated
|
||||
.rxrr_wait (elink1_rxrr_wait), // Templated
|
||||
.txwr_access (elink1_txwr_access), // Templated
|
||||
.txwr_packet (elink1_txwr_packet[PW-1:0]), // Templated
|
||||
.txrd_access (elink1_txrd_access), // Templated
|
||||
.txrd_packet (elink1_txrd_packet[PW-1:0]), // Templated
|
||||
.txrr_access (elink1_txrr_access), // Templated
|
||||
.txrr_packet (elink1_txrr_packet[PW-1:0])); // Templated
|
||||
|
||||
|
||||
|
||||
assign emem_access = elink1_rxwr_access | elink1_rxrd_access;
|
||||
|
||||
assign emem_packet[PW-1:0] = rxwr_access ? rxwr_packet[PW-1:0]:
|
||||
rxrd_packet[PW-1:0];
|
||||
assign emem_packet[PW-1:0] = elink1_rxwr_access ? elink1_rxwr_packet[PW-1:0]:
|
||||
elink1_rxrd_packet[PW-1:0];
|
||||
|
||||
assign rxrd_wait = emem_wait | rxwr_access;
|
||||
assign rxrd_wait = emem_wait | elink1_rxwr_access;
|
||||
|
||||
/*ememory AUTO_TEMPLATE (
|
||||
// Outputs
|
||||
.\(.*\)_out (txrr_\1[]),
|
||||
.\(.*\)_out (elink1_txrr_\1[]),
|
||||
.\(.*\)_in (emem_\1[]),
|
||||
.wait_out (emem_wait),
|
||||
);
|
||||
@ -202,8 +303,8 @@ module dv_elink(/*AUTOARG*/
|
||||
.wait_out (emem_wait),
|
||||
/*AUTOINST*/
|
||||
// Outputs
|
||||
.access_out (txrr_access), // Templated
|
||||
.packet_out (txrr_packet[PW-1:0]), // Templated
|
||||
.access_out (elink1_txrr_access), // Templated
|
||||
.packet_out (elink1_txrr_packet[PW-1:0]), // Templated
|
||||
// Inputs
|
||||
.reset (reset),
|
||||
.access_in (emem_access), // Templated
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user