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Adding debug logic to elink

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- packet capture register
- transaction counter logic
This commit is contained in:
Andreas Olofsson 2015-11-25 21:53:33 -05:00
parent 909b6337d1
commit e5163d4d82
4 changed files with 56 additions and 41 deletions
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1
elink/hdl/elink_regmap.v
View File

@ -25,6 +25,7 @@
`define ETX_STATUS 6'd5 //F0214-tx status
`define ETX_GPIO 6'd6 //F0218-direct data for tx pins
`define ETX_MONITOR 6'd7 //F021C-transaction monitor
`define ETX_PACKET 6'd8 //F0220-packet sampler
//ERX-REGS
`define ERX_CFG 6'd0 //F0300-config

10
elink/hdl/erx_core.v
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@ -145,7 +145,6 @@ module erx_core (/*AUTOARG*/
.remap_base (remap_base[31:0]));
/************************************************************/
/*ELINK MEMORY MANAGEMENT UNIT */
/************************************************************/
@ -265,7 +264,14 @@ module erx_core (/*AUTOARG*/
);
*/
assign rx_status[15:0] = {16'b0};
assign rx_status[15:0] = {11'b0,
rx_rd_wait,
rx_wr_wait,
rxrr_wait,
rxrd_wait,
rxwr_wait
};
assign gpio_datain[8:0]=9'b0;
/*

20
elink/hdl/etx_cfg.v
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@ -9,7 +9,8 @@ module etx_cfg (/*AUTOARG*/
mi_dout, tx_enable, mmu_enable, gpio_enable, remap_enable,
burst_enable, gpio_data, ctrlmode, ctrlmode_bypass,
// Inputs
nreset, clk, mi_en, mi_we, mi_addr, mi_din, tx_status, tx_access
nreset, clk, mi_en, mi_we, mi_addr, mi_din, tx_status, etx_access,
etx_packet
);
/******************************/
@ -18,6 +19,7 @@ module etx_cfg (/*AUTOARG*/
parameter PW = 104;
parameter RFAW = 6;
parameter DEFAULT_VERSION = 16'h0000;
parameter ID = 999;
/******************************/
/*HARDWARE RESET (EXTERNAL) */
@ -45,8 +47,9 @@ module etx_cfg (/*AUTOARG*/
output burst_enable; // enables bursting
input [15:0] tx_status; // etx status signals
input tx_access; // for transaction counter
//
input etx_access; // for transaction counter
input [PW-1:0] etx_packet; // for transaction sampler
//sampled by tx_lclk (test)
output [8:0] gpio_data; // data for elink outputs (static)
@ -60,6 +63,7 @@ module etx_cfg (/*AUTOARG*/
reg [8:0] tx_gpio_reg;
reg [15:0] tx_status_reg;
reg [31:0] tx_monitor_reg;
reg [31:0] tx_packet_reg;
reg [31:0] mi_dout;
reg ecfg_access;
@ -139,7 +143,14 @@ module etx_cfg (/*AUTOARG*/
if (tx_monitor_write)
tx_monitor_reg[31:0] <= mi_din[31:0];
else
tx_monitor_reg[31:0] <= tx_monitor_reg[31:0] + tx_access;
tx_monitor_reg[31:0] <= tx_monitor_reg[31:0] + (etx_access & ~(etx_packet[39:28]==ID) & ~(|tx_status[7:6]));
//###########################
//# PACKET
//###########################
always @ (posedge clk)
if(etx_access & ~(etx_packet[39:28]==ID))
tx_packet_reg[31:0] <= etx_packet[39:8];
//###############################
//# DATA READBACK MUX
@ -153,6 +164,7 @@ module etx_cfg (/*AUTOARG*/
`ETX_GPIO: mi_dout[31:0] <= {23'b0, tx_gpio_reg[8:0]};
`ETX_STATUS: mi_dout[31:0] <= {16'b0, tx_status_reg[15:0]};
`ETX_MONITOR: mi_dout[31:0] <= {tx_monitor_reg[31:0]};
`ETX_PACKET: mi_dout[31:0] <= {tx_packet_reg[31:0]};
default: mi_dout[31:0] <= 32'd0;
endcase // case (mi_addr[RFAW+1:2])
else

60
elink/hdl/etx_protocol.v
View File

@ -13,10 +13,11 @@
module etx_protocol (/*AUTOARG*/
// Outputs
etx_rd_wait, etx_wr_wait, tx_data_slow, tx_frame_slow,
etx_rd_wait, etx_wr_wait, tx_burst, tx_access, tx_data_slow,
tx_frame_slow,
// Inputs
nreset, clk, etx_access, etx_packet, tx_enable, gpio_data,
gpio_enable, tx_rd_wait, tx_wr_wait
nreset, clk, etx_access, etx_packet, tx_enable, burst_enable,
gpio_data, gpio_enable, tx_rd_wait, tx_wr_wait
);
parameter PW = 104;
@ -36,10 +37,13 @@ module etx_protocol (/*AUTOARG*/
output etx_rd_wait;
output etx_wr_wait;
//Enble transmit
input tx_enable; //transmit enable
input [8:0] gpio_data; //TODO
input gpio_enable; //TODO
//Config interface
input tx_enable; //transmit enable
input burst_enable; //Enables bursting
input [8:0] gpio_data; //TODO
input gpio_enable; //TODO
output tx_burst; //for TXSTATUS
output tx_access; //for TXMON
//Interface to IO
output [63:0] tx_data_slow;
@ -47,9 +51,9 @@ module etx_protocol (/*AUTOARG*/
input tx_rd_wait;
input tx_wr_wait;
//###################################################################
//################################################################
//# Local regs & wires
//###################################################################
//################################################################
reg [2:0] tx_state;
reg [PW-1:0] tx_packet;
wire etx_write;
@ -110,16 +114,17 @@ module etx_protocol (/*AUTOARG*/
assign burst_addr_match = ((tx_dstaddr[31:0]+32'h8) == etx_dstaddr[31:0]);
assign current_match = tx_access &
tx_write &
tx_write &
(tx_datamode[1:0]==2'b11) &
(tx_ctrlmode[3:0]==4'b0000);
assign next_match = etx_access &
assign next_match = etx_access & //BUG: should be valid?
etx_write &
(etx_datamode[1:0]==2'b11) &
(etx_ctrlmode[3:0]==4'b0000);
assign tx_burst = ~tx_wait &
assign tx_burst = burst_enable &
~tx_wait &
current_match &
next_match &
burst_addr_match;
@ -131,7 +136,10 @@ module etx_protocol (/*AUTOARG*/
//############################################################
//# TRANSMIT STATE MACHINE
//#############################################################
assign etx_valid = tx_enable & etx_access & ~tx_wait;
assign etx_valid = tx_enable &
etx_access &
~(etx_dstaddr[31:20]==ID) &
~tx_wait;
`define TX_IDLE 3'b000
`define TX_START 3'b001
@ -147,13 +155,15 @@ module etx_protocol (/*AUTOARG*/
`TX_IDLE: tx_state[2:0] <= etx_valid ? `TX_START : `TX_IDLE;
`TX_START: tx_state[2:0] <= `TX_ACK;
`TX_ACK: tx_state[2:0] <= tx_burst ? `TX_BURST :
etx_valid ? `TX_START :
`TX_IDLE;
etx_valid ? `TX_START :
`TX_IDLE;
`TX_BURST: tx_state[2:0] <= tx_burst ? `TX_BURST : `TX_IDLE;
endcase // case (tx_state[2:0])
assign tx_ack_wait = (tx_state[1:0]==`TX_START);
assign tx_access = (tx_state[1:0]==`TX_START);
assign tx_access = (tx_state[1:0]==`TX_START) |
(tx_state[1:0]==`TX_BURST);
//#######################################
//# Wait propagation circuit backwards
@ -161,7 +171,6 @@ module etx_protocol (/*AUTOARG*/
wire [63:0] tx_cycle1;
wire [63:0] tx_cycle2;
assign tx_frame_slow[3:0] = (tx_state[1:0]==`TX_START) ? 4'b0111 :
(tx_state[1:0]!=`TX_IDLE) ? 4'b1111 :
4'b0000;
@ -189,24 +198,11 @@ module etx_protocol (/*AUTOARG*/
//immediate wait for state machine
assign tx_wait = tx_wr_wait | tx_rd_wait;
//used to detect rising edge of wait signal
reg tx_wait_reg;
always @ (posedge clk)
tx_wait_reg <=tx_wait;
//simplify??
// assign adjust = //sage to sample new value on acknowledge
// ((tx_state[1:0]==`TX_ACK) & tx_wait);
//don't wait if there is nothing to wait for
// ((tx_state[1:0]==`TX_IDLE) & tx_wait & ~tx_wait_reg);
//wait for data
assign etx_wr_wait = (tx_wr_wait | tx_ack_wait );// & ~adjust ;//& ~adjust
assign etx_rd_wait = (tx_rd_wait | tx_ack_wait );// & ~adjust ;//& ~adjust
assign etx_wr_wait = (tx_wr_wait | tx_ack_wait );
assign etx_rd_wait = (tx_rd_wait | tx_ack_wait );
assign etx_wait = etx_wr_wait | etx_rd_wait;
endmodule // etx_protocol
// Local Variables:
// verilog-library-directories:("." "../../common/hdl")