mirror of
https://github.com/aolofsson/oh.git
synced 2025-01-30 02:32:53 +08:00
Changing parameter back to NMIO
- While N is a nice generic parameter, when integrating with a lot of other modules, it was becoming too confusing. The MIO already has three parameters: MPW, PW, and MIO. Important to keep them apart when integrating at the chip level.
This commit is contained in:
Andreas Olofsson
parent
4b87fdae34
commit
e5665a5bc0
@ -12,48 +12,48 @@ module mio (/*AUTOARG*/
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//#####################################################################
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//parameters
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parameter N = 8; // Mini IO width
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parameter AW = 32; // address width
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localparam PW = 2*AW+40; // emesh packet width
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parameter MPW = 128; // mio packet width (>PW)
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parameter DEF_CFG = 0; // Default config
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parameter DEF_CLK = 0; // Default clock
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parameter TARGET = "GENERIC"; // GENERIC,XILINX,ALTERA,GENERIC,ASIC
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parameter NMIO = 8; // IO width
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parameter AW = 32; // address width
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localparam PW = 2*AW+40; // emesh packet width
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parameter MPW = 128; // mio packet width (>PW)
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parameter DEF_CFG = 0; // Default config
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parameter DEF_CLK = 0; // Default clock
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parameter TARGET = "GENERIC";// GENERIC,XILINX,ALTERA,GENERIC,ASIC
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// reset, clk, config
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input clk; // main core clock
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input nreset; // async active low reset
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input clk; // main core clock
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input nreset; // async active low reset
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// tx chip interface (to IO)
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output tx_clk; // phase shited io_clk
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output tx_access; // access signal for IO
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output [N-1:0] tx_packet; // packet for IO
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input tx_wait; // pushback from IO
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output tx_clk; // phase shited io_clk
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output tx_access; // access signal for IO
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output [NMIO-1:0] tx_packet; // packet for IO
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input tx_wait; // pushback from IO
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// rx chip interface (from IO)
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input rx_clk; // rx clock
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input rx_access; // rx access
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input [N-1:0] rx_packet; // rx packet
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output rx_wait; // pushback from IO
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input rx_clk; // rx clock
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input rx_access; // rx access
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input [NMIO-1:0] rx_packet; // rx packet
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output rx_wait; // pushback from IO
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// core emesh interface
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input access_in; // access for tx
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input [PW-1:0] packet_in; // access for tx
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output wait_out; // access from tx fifo
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output access_out; // access from rx
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output [PW-1:0] packet_out; // packet from rx
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input wait_in; // pushback for rx fifo
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input access_in; // access for tx
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input [PW-1:0] packet_in; // access for tx
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output wait_out; // access from tx fifo
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output access_out; // access from rx
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output [PW-1:0] packet_out; // packet from rx
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input wait_in; // pushback for rx fifo
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// register config interface
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input reg_access_in; // config register access
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input [PW-1:0] reg_packet_in; // config register packet
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output reg_wait_out; // pushback by register read
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output reg_access_out;// config readback
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output [PW-1:0] reg_packet_out;// config reacback packet
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input reg_wait_in; // pushback for readback
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input reg_access_in; // config register access
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input [PW-1:0] reg_packet_in; // config register packet
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output reg_wait_out; // pushback by register read
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output reg_access_out;// config readback
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output [PW-1:0] reg_packet_out;// config reacback packet
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input reg_wait_in; // pushback for readback
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//#####################################################################
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//# BODY
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//#####################################################################
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@ -172,7 +172,7 @@ module mio (/*AUTOARG*/
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*/
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mio_dp #(.TARGET(TARGET),
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.N(N),
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.NMIO(NMIO),
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.PW(MPW))
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mio_dp(/*AUTOINST*/
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// Outputs
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@ -183,7 +183,7 @@ module mio (/*AUTOARG*/
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.rx_prog_full (rx_prog_full),
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.rx_empty (rx_empty),
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.tx_access (tx_access),
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.tx_packet (tx_packet[N-1:0]),
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.tx_packet (tx_packet[NMIO-1:0]),
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.rx_wait (rx_wait),
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.wait_out (tx_wait_io2c), // Templated
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.access_out (rx_access_io2c), // Templated
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@ -201,7 +201,7 @@ module mio (/*AUTOARG*/
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.tx_wait (tx_wait),
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.rx_clk (rx_clk),
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.rx_access (rx_access),
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.rx_packet (rx_packet[N-1:0]),
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.rx_packet (rx_packet[NMIO-1:0]),
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.access_in (tx_access_c2io), // Templated
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.packet_in (tx_packet_c2io[MPW-1:0]), // Templated
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.wait_in (rx_wait_c2io)); // Templated
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@ -14,53 +14,53 @@ module mio_dp (/*AUTOARG*/
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//parameters
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parameter PW = 104; // data width (core)
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parameter N = 8; // Mini IO width
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parameter NMIO = 8; // Mini IO width
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parameter TARGET = "GENERIC"; // GENERIC,XILINX,ALTERA,GENERIC,ASIC
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// reset, clk, config
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input clk; // main core clock
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input io_clk; // clock for TX
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input nreset; // async active low reset
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input [7:0] datasize; // size of data transmitted
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input ddr_mode; // dual data rate mode
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input lsbfirst; // send data lsbfirst
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input framepol; // polarity of frame signal
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input tx_en; // enable transmit
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input rx_en; // enable receive
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input clk; // main core clock
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input io_clk; // clock for TX
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input nreset; // async active low reset
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input [7:0] datasize; // size of data transmitted
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input ddr_mode; // dual data rate mode
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input lsbfirst; // send data lsbfirst
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input framepol; // polarity of frame signal
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input tx_en; // enable transmit
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input rx_en; // enable receive
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// status
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output tx_full;
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output tx_prog_full;
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output tx_empty;
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output rx_full;
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output rx_prog_full;
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output rx_empty;
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output tx_full;
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output tx_prog_full;
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output tx_empty;
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output rx_full;
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output rx_prog_full;
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output rx_empty;
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// tx interface
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output tx_access; // access signal for IO
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output [N-1:0] tx_packet; // packet for IO
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input tx_wait; // pushback from IO
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output tx_access; // access signal for IO
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output [NMIO-1:0] tx_packet; // packet for IO
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input tx_wait; // pushback from IO
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// rx interface
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input rx_clk; // rx clock
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input rx_access; // rx access
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input [N-1:0] rx_packet; // rx packet
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output rx_wait; // pushback from IO
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input rx_clk; // rx clock
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input rx_access; // rx access
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input [NMIO-1:0] rx_packet; // rx packet
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output rx_wait; // pushback from IO
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// core interface
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input access_in; // fifo data valid
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input [PW-1:0] packet_in; // fifo packet
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output wait_out; // wait pushback for fifo
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output access_out; // fifo data valid
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output [PW-1:0] packet_out; // fifo packet
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input wait_in; // wait pushback for fifo
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input access_in; // fifo data valid
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input [PW-1:0] packet_in; // fifo packet
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output wait_out; // wait pushback for fifo
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output access_out; // fifo data valid
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output [PW-1:0] packet_out; // fifo packet
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input wait_in; // wait pushback for fifo
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/*AUTOOUTPUT*/
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/*AUTOINPUT*/
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/*AUTOWIRE*/
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mtx #(.N(N),
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mtx #(.NMIO(NMIO),
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.PW(PW))
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mtx (/*AUTOINST*/
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// Outputs
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@ -69,7 +69,7 @@ module mio_dp (/*AUTOARG*/
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.tx_prog_full (tx_prog_full),
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.wait_out (wait_out),
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.tx_access (tx_access),
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.tx_packet (tx_packet[N-1:0]),
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.tx_packet (tx_packet[NMIO-1:0]),
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// Inputs
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.clk (clk),
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.io_clk (io_clk),
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@ -82,7 +82,7 @@ module mio_dp (/*AUTOARG*/
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.packet_in (packet_in[PW-1:0]),
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.tx_wait (tx_wait));
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mrx #(.N(N),
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mrx #(.NMIO(NMIO),
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.PW(PW))
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mrx (/*AUTOINST*/
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// Outputs
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@ -101,7 +101,7 @@ module mio_dp (/*AUTOARG*/
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.framepol (framepol),
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.rx_clk (rx_clk),
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.rx_access (rx_access),
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.rx_packet (rx_packet[N-1:0]),
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.rx_packet (rx_packet[NMIO-1:0]),
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.wait_in (wait_in));
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endmodule // mio_dp
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@ -16,7 +16,7 @@ module mio_if (/*AUTOARG*/
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//parameters
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parameter AW = 32; // address width
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parameter PW = 2*AW +40; // emesh packet width
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parameter MPW = PW+8; // mio packet width
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parameter MPW = 128; // mio packet width (> PW)
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// reset, clk, config
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input clk; // main core clock
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@ -13,33 +13,33 @@ module mrx (/*AUTOARG*/
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//parameters
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parameter PW = 104; // data width (core)
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parameter N = 8; // IO data width
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parameter NMIO = 8; // IO data width
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parameter FIFO_DEPTH = 32; // fifo depth
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parameter TARGET = "GENERIC"; // GENERIC,XILINX,ALTERA,GENERIC,ASIC
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//reset, clk, cfg
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input clk; // main core clock
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input nreset; // async active low reset
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input [7:0] datasize; // size of data transmitted (in bytes, 0=1 byte)
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input ddr_mode;
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input lsbfirst;
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input framepol;
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input clk; // main core clock
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input nreset; // async active low reset
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input [7:0] datasize; // size of data transmitted (in bytes, 0=1 byte)
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input ddr_mode;
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input lsbfirst;
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input framepol;
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//status
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output rx_empty; // rx fifo is empty
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output rx_full; // rx fifo is full (should never happen!)
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output rx_prog_full;// rx is getting full (stop sending!)
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output rx_empty; // rx fifo is empty
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output rx_full; // rx fifo is full (should never happen!)
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output rx_prog_full;// rx is getting full (stop sending!)
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//IO interface
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input rx_clk; // clock from IO
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input rx_access; // access signal for IO
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input [N-1:0] rx_packet; // packet from IO
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output rx_wait; // pushback for IO
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input rx_clk; // clock from IO
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input rx_access; // access signal for IO
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input [NMIO-1:0] rx_packet; // packet from IO
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output rx_wait; // pushback for IO
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// data
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output access_out; // fifo data valid
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output [PW-1:0] packet_out; // fifo packet
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input wait_in; // wait pushback for fifo
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output access_out; // fifo data valid
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output [PW-1:0] packet_out; // fifo packet
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input wait_in; // wait pushback for fifo
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//#####################################################################
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//# BODY
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@ -53,7 +53,7 @@ module mrx (/*AUTOARG*/
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wire fifo_access; // From mrx_protocol of mrx_protocol.v
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wire [PW-1:0] fifo_packet; // From mrx_protocol of mrx_protocol.v
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wire io_access; // From mrx_io of mrx_io.v
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wire [2*N-1:0] io_packet; // From mrx_io of mrx_io.v
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wire [2*NMIO-1:0] io_packet; // From mrx_io of mrx_io.v
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// End of automatics
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@ -104,7 +104,7 @@ module mrx (/*AUTOARG*/
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//########################################
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mrx_protocol #(.PW(PW),
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.N(N))
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.NMIO(NMIO))
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mrx_protocol (/*AUTOINST*/
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// Outputs
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.fifo_access (fifo_access),
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@ -115,25 +115,25 @@ module mrx (/*AUTOARG*/
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.datasize (datasize[7:0]),
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.lsbfirst (lsbfirst),
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.io_access (io_access),
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.io_packet (io_packet[2*N-1:0]));
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.io_packet (io_packet[2*NMIO-1:0]));
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//########################################
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//# FAST IO (DDR)
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//########################################
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mrx_io #(.N(N))
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mrx_io #(.NMIO(NMIO))
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mrx_io (
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/*AUTOINST*/
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// Outputs
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.io_access (io_access),
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.io_packet (io_packet[2*N-1:0]),
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.io_packet (io_packet[2*NMIO-1:0]),
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// Inputs
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.nreset (nreset),
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.rx_clk (rx_clk),
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.ddr_mode (ddr_mode),
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.lsbfirst (lsbfirst),
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.framepol (framepol),
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.rx_packet (rx_packet[N-1:0]),
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.rx_packet (rx_packet[NMIO-1:0]),
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.rx_access (rx_access));
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endmodule // ctx
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@ -13,28 +13,32 @@ module mrx_io (/*AUTOARG*/
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//#####################################################################
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//parameters
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parameter N = 16;
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parameter NMIO = 16;
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//RESET
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input nreset; // async active low reset
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input rx_clk; // clock for IO
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input ddr_mode; // select between sdr/ddr data
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input lsbfirst; // shufle data in msbfirst mode
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input framepol; // frame polarity
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input nreset; // async active low reset
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input rx_clk; // clock for IO
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input ddr_mode; // select between sdr/ddr data
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input lsbfirst; // shufle data in msbfirst mode
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input framepol; // frame polarity
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//IO interface
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input [N-1:0] rx_packet; // data for IO
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input rx_access; // access signal for IO
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input [NMIO-1:0] rx_packet; // data for IO
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input rx_access; // access signal for IO
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//FIFO interface (core side)
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output io_access; // fifo packet valid
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output [2*N-1:0] io_packet; // fifo packet
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output io_access; // fifo packet valid
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output [2*NMIO-1:0] io_packet; // fifo packet
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//#####################################################################
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//# BODY
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//#####################################################################
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//regs
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reg io_access;
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wire [2*N-1:0] ddr_data;
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reg [2*N-1:0] sdr_data;
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reg byte0_sel;
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reg io_access;
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wire [2*NMIO-1:0] ddr_data;
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reg [2*NMIO-1:0] sdr_data;
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reg byte0_sel;
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//########################################
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//# CLOCK, RESET
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@ -66,12 +70,12 @@ module mrx_io (/*AUTOARG*/
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//# DATA (DDR)
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//########################################
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oh_iddr #(.DW(N))
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data_iddr(.q1 (ddr_data[N-1:0]),
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.q2 (ddr_data[2*N-1:N]),
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oh_iddr #(.DW(NMIO))
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data_iddr(.q1 (ddr_data[NMIO-1:0]),
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.q2 (ddr_data[2*NMIO-1:NMIO]),
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.clk (rx_clk),
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.ce (rx_frame),
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.din (rx_packet[N-1:0])
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.din (rx_packet[NMIO-1:0])
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);
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//########################################
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//# DATA (SDR)
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@ -86,18 +90,18 @@ module mrx_io (/*AUTOARG*/
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always @ (posedge rx_clk)
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if(byte0_sel)
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sdr_data[N-1:0] <= rx_packet[N-1:0];
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sdr_data[NMIO-1:0] <= rx_packet[NMIO-1:0];
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else
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sdr_data[2*N-1:N] <= rx_packet[N-1:0];
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sdr_data[2*NMIO-1:NMIO] <= rx_packet[NMIO-1:0];
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//########################################
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//# HANDL DDR/SDR
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//########################################
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assign io_packet[2*N-1:0] = ~ddr_mode ? sdr_data[2*N-1:0] :
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ddr_mode & ~lsbfirst ? {ddr_data[N-1:0],
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ddr_data[2*N-1:N]} :
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ddr_data[2*N-1:0];
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assign io_packet[2*NMIO-1:0] = ~ddr_mode ? sdr_data[2*NMIO-1:0] :
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ddr_mode & ~lsbfirst ? {ddr_data[NMIO-1:0],
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ddr_data[2*NMIO-1:NMIO]} :
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ddr_data[2*NMIO-1:0];
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endmodule // mrx_io
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@ -10,25 +10,25 @@ module mrx_protocol (/*AUTOARG*/
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//#####################################################################
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//parameters
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parameter PW = 104; // packet width (core)
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parameter N = 16; // io packet width
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localparam CW = $clog2(2*PW/N); // transfer count width
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parameter PW = 104; // packet width (core)
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parameter NMIO = 8; // io packet width
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localparam CW = $clog2(2*PW/NMIO); // transfer count width
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//clock and reset
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input rx_clk; // rx clock
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input nreset; // async active low reset
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input rx_clk; // rx clock
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input nreset; // async active low reset
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//config
|
||||
input [7:0] datasize; // dynamic width of output data
|
||||
input lsbfirst;
|
||||
|
||||
input [7:0] datasize; // dynamic width of output data
|
||||
input lsbfirst;
|
||||
|
||||
//16 bit interface
|
||||
input io_access; // access signal from IO
|
||||
input [2*N-1:0] io_packet; // data from IO
|
||||
input io_access; // access signal from IO
|
||||
input [2*NMIO-1:0] io_packet; // data from IO
|
||||
|
||||
//wide input interface
|
||||
output fifo_access; // access for fifo
|
||||
output [PW-1:0] fifo_packet; // packet for fifo
|
||||
output fifo_access; // access for fifo
|
||||
output [PW-1:0] fifo_packet; // packet for fifo
|
||||
|
||||
//#####################################################################
|
||||
//# BODY
|
||||
@ -78,13 +78,13 @@ module mrx_protocol (/*AUTOARG*/
|
||||
//##########################
|
||||
|
||||
oh_ser2par #(.PW(PW),
|
||||
.SW(2*N))
|
||||
.SW(2*NMIO))
|
||||
|
||||
ser2par (// Outputs
|
||||
.dout (fifo_packet[PW-1:0]),
|
||||
// Inputs
|
||||
.clk (rx_clk),
|
||||
.din (io_packet),
|
||||
.din (io_packet[2*NMIO-1:0]),
|
||||
.lsbfirst (lsbfirst),
|
||||
.shift (shift)
|
||||
);
|
||||
|
||||
@ -13,34 +13,34 @@ module mtx (/*AUTOARG*/
|
||||
|
||||
//parameters
|
||||
parameter PW = 104; // data width (core)
|
||||
parameter N = 16; // IO data width
|
||||
parameter NMIO = 8; // IO data width
|
||||
parameter FIFO_DEPTH = 32; // fifo depth
|
||||
parameter TARGET = "GENERIC"; // GENERIC,XILINX,ALTERA,GENERIC,ASIC
|
||||
localparam CW = $clog2(2*PW/N); // transfer count width
|
||||
localparam CW = $clog2(2*PW/NMIO); // transfer count width
|
||||
|
||||
//reset, clk, cfg
|
||||
input clk; // main core clock
|
||||
input io_clk; // clock for tx logic
|
||||
input nreset; // async active low reset
|
||||
input tx_en; // transmit enable
|
||||
input [7:0] datasize; // size of data transmitted/received
|
||||
input ddr_mode; // configure mio in ddr mode
|
||||
input lsbfirst; // send bits lsb first
|
||||
input clk; // main core clock
|
||||
input io_clk; // clock for tx logic
|
||||
input nreset; // async active low reset
|
||||
input tx_en; // transmit enable
|
||||
input [7:0] datasize; // size of data transmitted/received
|
||||
input ddr_mode; // configure mio in ddr mode
|
||||
input lsbfirst; // send bits lsb first
|
||||
|
||||
//status
|
||||
output tx_empty; // tx fifo is empty
|
||||
output tx_full; // tx fifo is full (should never happen!)
|
||||
output tx_prog_full;// tx is getting full (stop sending!)
|
||||
output tx_empty; // tx fifo is empty
|
||||
output tx_full; // tx fifo is full (should never happen!)
|
||||
output tx_prog_full;// tx is getting full (stop sending!)
|
||||
|
||||
// data to transmit
|
||||
input access_in; // fifo data valid
|
||||
input [PW-1:0] packet_in; // fifo packet
|
||||
output wait_out; // wait pushback for fifo
|
||||
input access_in; // fifo data valid
|
||||
input [PW-1:0] packet_in; // fifo packet
|
||||
output wait_out; // wait pushback for fifo
|
||||
|
||||
//IO interface (90 deg clock supplied outside this block)
|
||||
output tx_access; // access signal for IO
|
||||
output [N-1:0] tx_packet; // packet for IO
|
||||
input tx_wait; // pushback from IO
|
||||
output tx_access; // access signal for IO
|
||||
output [NMIO-1:0] tx_packet; // packet for IO
|
||||
input tx_wait; // pushback from IO
|
||||
|
||||
//#####################################################################
|
||||
//# BODY
|
||||
@ -54,7 +54,7 @@ module mtx (/*AUTOARG*/
|
||||
wire [PW-1:0] fifo_packet; // From fifo of oh_fifo_cdc.v
|
||||
wire fifo_wait; // From par2ser of oh_par2ser.v
|
||||
wire io_access; // From par2ser of oh_par2ser.v
|
||||
wire [2*N-1:0] io_packet; // From par2ser of oh_par2ser.v
|
||||
wire [2*NMIO-1:0] io_packet; // From par2ser of oh_par2ser.v
|
||||
wire io_wait; // From mtx_io of mtx_io.v
|
||||
// End of automatics
|
||||
|
||||
@ -104,7 +104,7 @@ module mtx (/*AUTOARG*/
|
||||
//########################################
|
||||
|
||||
/*oh_par2ser AUTO_TEMPLATE (// outputs
|
||||
.dout (io_packet[2*N-1:0]),
|
||||
.dout (io_packet[2*NMIO-1:0]),
|
||||
.access_out (io_access),
|
||||
.wait_out (fifo_wait),
|
||||
// inputs
|
||||
@ -121,10 +121,10 @@ module mtx (/*AUTOARG*/
|
||||
*/
|
||||
|
||||
oh_par2ser #(.PW(PW),
|
||||
.SW(2*N))
|
||||
.SW(2*NMIO))
|
||||
par2ser (/*AUTOINST*/
|
||||
// Outputs
|
||||
.dout (io_packet[2*N-1:0]), // Templated
|
||||
.dout (io_packet[2*NMIO-1:0]), // Templated
|
||||
.access_out (io_access), // Templated
|
||||
.wait_out (fifo_wait), // Templated
|
||||
// Inputs
|
||||
@ -142,10 +142,10 @@ module mtx (/*AUTOARG*/
|
||||
//# FAST IO (DDR)
|
||||
//########################################
|
||||
|
||||
mtx_io #(.N(N))
|
||||
mtx_io #(.NMIO(NMIO))
|
||||
mtx_io (/*AUTOINST*/
|
||||
// Outputs
|
||||
.tx_packet (tx_packet[N-1:0]),
|
||||
.tx_packet (tx_packet[NMIO-1:0]),
|
||||
.tx_access (tx_access),
|
||||
.io_wait (io_wait),
|
||||
// Inputs
|
||||
@ -155,7 +155,7 @@ module mtx (/*AUTOARG*/
|
||||
.lsbfirst (lsbfirst),
|
||||
.tx_wait (tx_wait),
|
||||
.io_access (io_access),
|
||||
.io_packet (io_packet[2*N-1:0]));
|
||||
.io_packet (io_packet[2*NMIO-1:0]));
|
||||
|
||||
endmodule // mtx
|
||||
// Local Variables:
|
||||
|
||||
@ -13,30 +13,34 @@ module mtx_io (/*AUTOARG*/
|
||||
//#####################################################################
|
||||
|
||||
//parameters
|
||||
parameter N = 16;
|
||||
parameter NMIO = 16;
|
||||
|
||||
//reset, clk, cfg
|
||||
input nreset; // async active low reset
|
||||
input io_clk; // clock from divider
|
||||
input ddr_mode; // send data as ddr
|
||||
input lsbfirst; // send data lsbfirst
|
||||
input nreset; // async active low reset
|
||||
input io_clk; // clock from divider
|
||||
input ddr_mode; // send data as ddr
|
||||
input lsbfirst; // send data lsbfirst
|
||||
|
||||
//IO interface
|
||||
output [N-1:0] tx_packet; // data for IO
|
||||
output tx_access; // access signal for IO
|
||||
input tx_wait; // IO wait signals
|
||||
output [NMIO-1:0] tx_packet; // data for IO
|
||||
output tx_access; // access signal for IO
|
||||
input tx_wait; // IO wait signals
|
||||
|
||||
//Core side
|
||||
input io_access; // valid packet
|
||||
input [2*N-1:0] io_packet; // packet
|
||||
output io_wait; // pushback to serializer in sdr mode
|
||||
input io_access; // valid packet
|
||||
input [2*NMIO-1:0] io_packet; // packet
|
||||
output io_wait; // pushback to serializer in sdr mode
|
||||
|
||||
//#####################################################################
|
||||
//# BODYINTER
|
||||
//#####################################################################
|
||||
|
||||
//regs
|
||||
reg tx_access;
|
||||
wire [N-1:0] tx_packet_ddr;
|
||||
reg [N-1:0] tx_packet_sdr;
|
||||
reg byte0_sel;
|
||||
wire [2*N-1:0] ddr_data;
|
||||
reg tx_access;
|
||||
wire [NMIO-1:0] tx_packet_ddr;
|
||||
reg [NMIO-1:0] tx_packet_sdr;
|
||||
reg byte0_sel;
|
||||
wire [2*NMIO-1:0] ddr_data;
|
||||
|
||||
//########################################
|
||||
//# RESET
|
||||
@ -64,8 +68,8 @@ module mtx_io (/*AUTOARG*/
|
||||
// sampling data for sdr
|
||||
always @ (posedge io_clk)
|
||||
if(io_access)
|
||||
tx_packet_sdr[N-1:0] <= byte0_sel ? io_packet[N-1:0] :
|
||||
io_packet[2*N-1:N];
|
||||
tx_packet_sdr[NMIO-1:0] <= byte0_sel ? io_packet[NMIO-1:0] :
|
||||
io_packet[2*NMIO-1:NMIO];
|
||||
|
||||
//select 2nd byte (stall on this signal)
|
||||
always @ (posedge io_clk)
|
||||
@ -82,20 +86,20 @@ module mtx_io (/*AUTOARG*/
|
||||
//########################################
|
||||
|
||||
// shuffle bits when in msb mode
|
||||
assign ddr_data[2*N-1:0] = (~lsbfirst & ddr_mode) ? {io_packet[N-1:0],
|
||||
io_packet[2*N-1:N]} :
|
||||
io_packet[2*N-1:0];
|
||||
oh_oddr#(.DW(N))
|
||||
data_oddr (.out (tx_packet_ddr[N-1:0]),
|
||||
assign ddr_data[2*NMIO-1:0] = (~lsbfirst & ddr_mode) ? {io_packet[NMIO-1:0],
|
||||
io_packet[2*NMIO-1:NMIO]} :
|
||||
io_packet[2*NMIO-1:0];
|
||||
oh_oddr#(.DW(NMIO))
|
||||
data_oddr (.out (tx_packet_ddr[NMIO-1:0]),
|
||||
.clk (io_clk),
|
||||
.ce (1'b1),
|
||||
.din1 (ddr_data[N-1:0]),
|
||||
.din2 (ddr_data[2*N-1:N])
|
||||
.din1 (ddr_data[NMIO-1:0]),
|
||||
.din2 (ddr_data[2*NMIO-1:NMIO])
|
||||
);
|
||||
|
||||
//select between ddr/sdr data
|
||||
assign tx_packet[N-1:0] = ddr_mode ? tx_packet_ddr[N-1:0] :
|
||||
tx_packet_sdr[N-1:0];
|
||||
assign tx_packet[NMIO-1:0] = ddr_mode ? tx_packet_ddr[NMIO-1:0] :
|
||||
tx_packet_sdr[NMIO-1:0];
|
||||
|
||||
endmodule // mtx_io
|
||||
// Local Variables:
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user