diff --git a/src/mio/hdl/mio.v b/src/mio/hdl/mio.v index 47ba338..1d05144 100644 --- a/src/mio/hdl/mio.v +++ b/src/mio/hdl/mio.v @@ -12,48 +12,48 @@ module mio (/*AUTOARG*/ //##################################################################### //parameters - parameter N = 8; // Mini IO width - parameter AW = 32; // address width - localparam PW = 2*AW+40; // emesh packet width - parameter MPW = 128; // mio packet width (>PW) - parameter DEF_CFG = 0; // Default config - parameter DEF_CLK = 0; // Default clock - parameter TARGET = "GENERIC"; // GENERIC,XILINX,ALTERA,GENERIC,ASIC + parameter NMIO = 8; // IO width + parameter AW = 32; // address width + localparam PW = 2*AW+40; // emesh packet width + parameter MPW = 128; // mio packet width (>PW) + parameter DEF_CFG = 0; // Default config + parameter DEF_CLK = 0; // Default clock + parameter TARGET = "GENERIC";// GENERIC,XILINX,ALTERA,GENERIC,ASIC // reset, clk, config - input clk; // main core clock - input nreset; // async active low reset + input clk; // main core clock + input nreset; // async active low reset // tx chip interface (to IO) - output tx_clk; // phase shited io_clk - output tx_access; // access signal for IO - output [N-1:0] tx_packet; // packet for IO - input tx_wait; // pushback from IO + output tx_clk; // phase shited io_clk + output tx_access; // access signal for IO + output [NMIO-1:0] tx_packet; // packet for IO + input tx_wait; // pushback from IO // rx chip interface (from IO) - input rx_clk; // rx clock - input rx_access; // rx access - input [N-1:0] rx_packet; // rx packet - output rx_wait; // pushback from IO - + input rx_clk; // rx clock + input rx_access; // rx access + input [NMIO-1:0] rx_packet; // rx packet + output rx_wait; // pushback from IO + // core emesh interface - input access_in; // access for tx - input [PW-1:0] packet_in; // access for tx - output wait_out; // access from tx fifo - - output access_out; // access from rx - output [PW-1:0] packet_out; // packet from rx - input wait_in; // pushback for rx fifo - + input access_in; // access for tx + input [PW-1:0] packet_in; // access for tx + output wait_out; // access from tx fifo + + output access_out; // access from rx + output [PW-1:0] packet_out; // packet from rx + input wait_in; // pushback for rx fifo + // register config interface - input reg_access_in; // config register access - input [PW-1:0] reg_packet_in; // config register packet - output reg_wait_out; // pushback by register read - - output reg_access_out;// config readback - output [PW-1:0] reg_packet_out;// config reacback packet - input reg_wait_in; // pushback for readback - + input reg_access_in; // config register access + input [PW-1:0] reg_packet_in; // config register packet + output reg_wait_out; // pushback by register read + + output reg_access_out;// config readback + output [PW-1:0] reg_packet_out;// config reacback packet + input reg_wait_in; // pushback for readback + //##################################################################### //# BODY //##################################################################### @@ -172,7 +172,7 @@ module mio (/*AUTOARG*/ */ mio_dp #(.TARGET(TARGET), - .N(N), + .NMIO(NMIO), .PW(MPW)) mio_dp(/*AUTOINST*/ // Outputs @@ -183,7 +183,7 @@ module mio (/*AUTOARG*/ .rx_prog_full (rx_prog_full), .rx_empty (rx_empty), .tx_access (tx_access), - .tx_packet (tx_packet[N-1:0]), + .tx_packet (tx_packet[NMIO-1:0]), .rx_wait (rx_wait), .wait_out (tx_wait_io2c), // Templated .access_out (rx_access_io2c), // Templated @@ -201,7 +201,7 @@ module mio (/*AUTOARG*/ .tx_wait (tx_wait), .rx_clk (rx_clk), .rx_access (rx_access), - .rx_packet (rx_packet[N-1:0]), + .rx_packet (rx_packet[NMIO-1:0]), .access_in (tx_access_c2io), // Templated .packet_in (tx_packet_c2io[MPW-1:0]), // Templated .wait_in (rx_wait_c2io)); // Templated diff --git a/src/mio/hdl/mio_dp.v b/src/mio/hdl/mio_dp.v index d05164e..5df8d1e 100644 --- a/src/mio/hdl/mio_dp.v +++ b/src/mio/hdl/mio_dp.v @@ -14,53 +14,53 @@ module mio_dp (/*AUTOARG*/ //parameters parameter PW = 104; // data width (core) - parameter N = 8; // Mini IO width + parameter NMIO = 8; // Mini IO width parameter TARGET = "GENERIC"; // GENERIC,XILINX,ALTERA,GENERIC,ASIC // reset, clk, config - input clk; // main core clock - input io_clk; // clock for TX - input nreset; // async active low reset - input [7:0] datasize; // size of data transmitted - input ddr_mode; // dual data rate mode - input lsbfirst; // send data lsbfirst - input framepol; // polarity of frame signal - input tx_en; // enable transmit - input rx_en; // enable receive + input clk; // main core clock + input io_clk; // clock for TX + input nreset; // async active low reset + input [7:0] datasize; // size of data transmitted + input ddr_mode; // dual data rate mode + input lsbfirst; // send data lsbfirst + input framepol; // polarity of frame signal + input tx_en; // enable transmit + input rx_en; // enable receive // status - output tx_full; - output tx_prog_full; - output tx_empty; - output rx_full; - output rx_prog_full; - output rx_empty; + output tx_full; + output tx_prog_full; + output tx_empty; + output rx_full; + output rx_prog_full; + output rx_empty; // tx interface - output tx_access; // access signal for IO - output [N-1:0] tx_packet; // packet for IO - input tx_wait; // pushback from IO + output tx_access; // access signal for IO + output [NMIO-1:0] tx_packet; // packet for IO + input tx_wait; // pushback from IO // rx interface - input rx_clk; // rx clock - input rx_access; // rx access - input [N-1:0] rx_packet; // rx packet - output rx_wait; // pushback from IO - + input rx_clk; // rx clock + input rx_access; // rx access + input [NMIO-1:0] rx_packet; // rx packet + output rx_wait; // pushback from IO + // core interface - input access_in; // fifo data valid - input [PW-1:0] packet_in; // fifo packet - output wait_out; // wait pushback for fifo - - output access_out; // fifo data valid - output [PW-1:0] packet_out; // fifo packet - input wait_in; // wait pushback for fifo + input access_in; // fifo data valid + input [PW-1:0] packet_in; // fifo packet + output wait_out; // wait pushback for fifo + + output access_out; // fifo data valid + output [PW-1:0] packet_out; // fifo packet + input wait_in; // wait pushback for fifo /*AUTOOUTPUT*/ /*AUTOINPUT*/ /*AUTOWIRE*/ - mtx #(.N(N), + mtx #(.NMIO(NMIO), .PW(PW)) mtx (/*AUTOINST*/ // Outputs @@ -69,7 +69,7 @@ module mio_dp (/*AUTOARG*/ .tx_prog_full (tx_prog_full), .wait_out (wait_out), .tx_access (tx_access), - .tx_packet (tx_packet[N-1:0]), + .tx_packet (tx_packet[NMIO-1:0]), // Inputs .clk (clk), .io_clk (io_clk), @@ -82,7 +82,7 @@ module mio_dp (/*AUTOARG*/ .packet_in (packet_in[PW-1:0]), .tx_wait (tx_wait)); - mrx #(.N(N), + mrx #(.NMIO(NMIO), .PW(PW)) mrx (/*AUTOINST*/ // Outputs @@ -101,7 +101,7 @@ module mio_dp (/*AUTOARG*/ .framepol (framepol), .rx_clk (rx_clk), .rx_access (rx_access), - .rx_packet (rx_packet[N-1:0]), + .rx_packet (rx_packet[NMIO-1:0]), .wait_in (wait_in)); endmodule // mio_dp diff --git a/src/mio/hdl/mio_if.v b/src/mio/hdl/mio_if.v index 3cd718d..ba16c27 100644 --- a/src/mio/hdl/mio_if.v +++ b/src/mio/hdl/mio_if.v @@ -16,7 +16,7 @@ module mio_if (/*AUTOARG*/ //parameters parameter AW = 32; // address width parameter PW = 2*AW +40; // emesh packet width - parameter MPW = PW+8; // mio packet width + parameter MPW = 128; // mio packet width (> PW) // reset, clk, config input clk; // main core clock diff --git a/src/mio/hdl/mrx.v b/src/mio/hdl/mrx.v index aa7bc05..3781e77 100644 --- a/src/mio/hdl/mrx.v +++ b/src/mio/hdl/mrx.v @@ -13,33 +13,33 @@ module mrx (/*AUTOARG*/ //parameters parameter PW = 104; // data width (core) - parameter N = 8; // IO data width + parameter NMIO = 8; // IO data width parameter FIFO_DEPTH = 32; // fifo depth parameter TARGET = "GENERIC"; // GENERIC,XILINX,ALTERA,GENERIC,ASIC //reset, clk, cfg - input clk; // main core clock - input nreset; // async active low reset - input [7:0] datasize; // size of data transmitted (in bytes, 0=1 byte) - input ddr_mode; - input lsbfirst; - input framepol; + input clk; // main core clock + input nreset; // async active low reset + input [7:0] datasize; // size of data transmitted (in bytes, 0=1 byte) + input ddr_mode; + input lsbfirst; + input framepol; //status - output rx_empty; // rx fifo is empty - output rx_full; // rx fifo is full (should never happen!) - output rx_prog_full;// rx is getting full (stop sending!) + output rx_empty; // rx fifo is empty + output rx_full; // rx fifo is full (should never happen!) + output rx_prog_full;// rx is getting full (stop sending!) //IO interface - input rx_clk; // clock from IO - input rx_access; // access signal for IO - input [N-1:0] rx_packet; // packet from IO - output rx_wait; // pushback for IO + input rx_clk; // clock from IO + input rx_access; // access signal for IO + input [NMIO-1:0] rx_packet; // packet from IO + output rx_wait; // pushback for IO // data - output access_out; // fifo data valid - output [PW-1:0] packet_out; // fifo packet - input wait_in; // wait pushback for fifo + output access_out; // fifo data valid + output [PW-1:0] packet_out; // fifo packet + input wait_in; // wait pushback for fifo //##################################################################### //# BODY @@ -53,7 +53,7 @@ module mrx (/*AUTOARG*/ wire fifo_access; // From mrx_protocol of mrx_protocol.v wire [PW-1:0] fifo_packet; // From mrx_protocol of mrx_protocol.v wire io_access; // From mrx_io of mrx_io.v - wire [2*N-1:0] io_packet; // From mrx_io of mrx_io.v + wire [2*NMIO-1:0] io_packet; // From mrx_io of mrx_io.v // End of automatics @@ -104,7 +104,7 @@ module mrx (/*AUTOARG*/ //######################################## mrx_protocol #(.PW(PW), - .N(N)) + .NMIO(NMIO)) mrx_protocol (/*AUTOINST*/ // Outputs .fifo_access (fifo_access), @@ -115,25 +115,25 @@ module mrx (/*AUTOARG*/ .datasize (datasize[7:0]), .lsbfirst (lsbfirst), .io_access (io_access), - .io_packet (io_packet[2*N-1:0])); + .io_packet (io_packet[2*NMIO-1:0])); //######################################## //# FAST IO (DDR) //######################################## - mrx_io #(.N(N)) + mrx_io #(.NMIO(NMIO)) mrx_io ( /*AUTOINST*/ // Outputs .io_access (io_access), - .io_packet (io_packet[2*N-1:0]), + .io_packet (io_packet[2*NMIO-1:0]), // Inputs .nreset (nreset), .rx_clk (rx_clk), .ddr_mode (ddr_mode), .lsbfirst (lsbfirst), .framepol (framepol), - .rx_packet (rx_packet[N-1:0]), + .rx_packet (rx_packet[NMIO-1:0]), .rx_access (rx_access)); endmodule // ctx diff --git a/src/mio/hdl/mrx_io.v b/src/mio/hdl/mrx_io.v index bec1266..8600eb7 100644 --- a/src/mio/hdl/mrx_io.v +++ b/src/mio/hdl/mrx_io.v @@ -13,28 +13,32 @@ module mrx_io (/*AUTOARG*/ //##################################################################### //parameters - parameter N = 16; + parameter NMIO = 16; //RESET - input nreset; // async active low reset - input rx_clk; // clock for IO - input ddr_mode; // select between sdr/ddr data - input lsbfirst; // shufle data in msbfirst mode - input framepol; // frame polarity + input nreset; // async active low reset + input rx_clk; // clock for IO + input ddr_mode; // select between sdr/ddr data + input lsbfirst; // shufle data in msbfirst mode + input framepol; // frame polarity //IO interface - input [N-1:0] rx_packet; // data for IO - input rx_access; // access signal for IO + input [NMIO-1:0] rx_packet; // data for IO + input rx_access; // access signal for IO //FIFO interface (core side) - output io_access; // fifo packet valid - output [2*N-1:0] io_packet; // fifo packet - + output io_access; // fifo packet valid + output [2*NMIO-1:0] io_packet; // fifo packet + + //##################################################################### + //# BODY + //##################################################################### + //regs - reg io_access; - wire [2*N-1:0] ddr_data; - reg [2*N-1:0] sdr_data; - reg byte0_sel; + reg io_access; + wire [2*NMIO-1:0] ddr_data; + reg [2*NMIO-1:0] sdr_data; + reg byte0_sel; //######################################## //# CLOCK, RESET @@ -66,12 +70,12 @@ module mrx_io (/*AUTOARG*/ //# DATA (DDR) //######################################## - oh_iddr #(.DW(N)) - data_iddr(.q1 (ddr_data[N-1:0]), - .q2 (ddr_data[2*N-1:N]), + oh_iddr #(.DW(NMIO)) + data_iddr(.q1 (ddr_data[NMIO-1:0]), + .q2 (ddr_data[2*NMIO-1:NMIO]), .clk (rx_clk), .ce (rx_frame), - .din (rx_packet[N-1:0]) + .din (rx_packet[NMIO-1:0]) ); //######################################## //# DATA (SDR) @@ -86,18 +90,18 @@ module mrx_io (/*AUTOARG*/ always @ (posedge rx_clk) if(byte0_sel) - sdr_data[N-1:0] <= rx_packet[N-1:0]; + sdr_data[NMIO-1:0] <= rx_packet[NMIO-1:0]; else - sdr_data[2*N-1:N] <= rx_packet[N-1:0]; + sdr_data[2*NMIO-1:NMIO] <= rx_packet[NMIO-1:0]; //######################################## //# HANDL DDR/SDR //######################################## - assign io_packet[2*N-1:0] = ~ddr_mode ? sdr_data[2*N-1:0] : - ddr_mode & ~lsbfirst ? {ddr_data[N-1:0], - ddr_data[2*N-1:N]} : - ddr_data[2*N-1:0]; + assign io_packet[2*NMIO-1:0] = ~ddr_mode ? sdr_data[2*NMIO-1:0] : + ddr_mode & ~lsbfirst ? {ddr_data[NMIO-1:0], + ddr_data[2*NMIO-1:NMIO]} : + ddr_data[2*NMIO-1:0]; endmodule // mrx_io diff --git a/src/mio/hdl/mrx_protocol.v b/src/mio/hdl/mrx_protocol.v index 76f714b..2f03167 100644 --- a/src/mio/hdl/mrx_protocol.v +++ b/src/mio/hdl/mrx_protocol.v @@ -10,25 +10,25 @@ module mrx_protocol (/*AUTOARG*/ //##################################################################### //parameters - parameter PW = 104; // packet width (core) - parameter N = 16; // io packet width - localparam CW = $clog2(2*PW/N); // transfer count width + parameter PW = 104; // packet width (core) + parameter NMIO = 8; // io packet width + localparam CW = $clog2(2*PW/NMIO); // transfer count width //clock and reset - input rx_clk; // rx clock - input nreset; // async active low reset + input rx_clk; // rx clock + input nreset; // async active low reset //config - input [7:0] datasize; // dynamic width of output data - input lsbfirst; - + input [7:0] datasize; // dynamic width of output data + input lsbfirst; + //16 bit interface - input io_access; // access signal from IO - input [2*N-1:0] io_packet; // data from IO + input io_access; // access signal from IO + input [2*NMIO-1:0] io_packet; // data from IO //wide input interface - output fifo_access; // access for fifo - output [PW-1:0] fifo_packet; // packet for fifo + output fifo_access; // access for fifo + output [PW-1:0] fifo_packet; // packet for fifo //##################################################################### //# BODY @@ -78,13 +78,13 @@ module mrx_protocol (/*AUTOARG*/ //########################## oh_ser2par #(.PW(PW), - .SW(2*N)) + .SW(2*NMIO)) ser2par (// Outputs .dout (fifo_packet[PW-1:0]), // Inputs .clk (rx_clk), - .din (io_packet), + .din (io_packet[2*NMIO-1:0]), .lsbfirst (lsbfirst), .shift (shift) ); diff --git a/src/mio/hdl/mtx.v b/src/mio/hdl/mtx.v index dfb3c7c..da25ee5 100644 --- a/src/mio/hdl/mtx.v +++ b/src/mio/hdl/mtx.v @@ -13,34 +13,34 @@ module mtx (/*AUTOARG*/ //parameters parameter PW = 104; // data width (core) - parameter N = 16; // IO data width + parameter NMIO = 8; // IO data width parameter FIFO_DEPTH = 32; // fifo depth parameter TARGET = "GENERIC"; // GENERIC,XILINX,ALTERA,GENERIC,ASIC - localparam CW = $clog2(2*PW/N); // transfer count width + localparam CW = $clog2(2*PW/NMIO); // transfer count width //reset, clk, cfg - input clk; // main core clock - input io_clk; // clock for tx logic - input nreset; // async active low reset - input tx_en; // transmit enable - input [7:0] datasize; // size of data transmitted/received - input ddr_mode; // configure mio in ddr mode - input lsbfirst; // send bits lsb first + input clk; // main core clock + input io_clk; // clock for tx logic + input nreset; // async active low reset + input tx_en; // transmit enable + input [7:0] datasize; // size of data transmitted/received + input ddr_mode; // configure mio in ddr mode + input lsbfirst; // send bits lsb first //status - output tx_empty; // tx fifo is empty - output tx_full; // tx fifo is full (should never happen!) - output tx_prog_full;// tx is getting full (stop sending!) + output tx_empty; // tx fifo is empty + output tx_full; // tx fifo is full (should never happen!) + output tx_prog_full;// tx is getting full (stop sending!) // data to transmit - input access_in; // fifo data valid - input [PW-1:0] packet_in; // fifo packet - output wait_out; // wait pushback for fifo + input access_in; // fifo data valid + input [PW-1:0] packet_in; // fifo packet + output wait_out; // wait pushback for fifo //IO interface (90 deg clock supplied outside this block) - output tx_access; // access signal for IO - output [N-1:0] tx_packet; // packet for IO - input tx_wait; // pushback from IO + output tx_access; // access signal for IO + output [NMIO-1:0] tx_packet; // packet for IO + input tx_wait; // pushback from IO //##################################################################### //# BODY @@ -54,7 +54,7 @@ module mtx (/*AUTOARG*/ wire [PW-1:0] fifo_packet; // From fifo of oh_fifo_cdc.v wire fifo_wait; // From par2ser of oh_par2ser.v wire io_access; // From par2ser of oh_par2ser.v - wire [2*N-1:0] io_packet; // From par2ser of oh_par2ser.v + wire [2*NMIO-1:0] io_packet; // From par2ser of oh_par2ser.v wire io_wait; // From mtx_io of mtx_io.v // End of automatics @@ -104,7 +104,7 @@ module mtx (/*AUTOARG*/ //######################################## /*oh_par2ser AUTO_TEMPLATE (// outputs - .dout (io_packet[2*N-1:0]), + .dout (io_packet[2*NMIO-1:0]), .access_out (io_access), .wait_out (fifo_wait), // inputs @@ -121,10 +121,10 @@ module mtx (/*AUTOARG*/ */ oh_par2ser #(.PW(PW), - .SW(2*N)) + .SW(2*NMIO)) par2ser (/*AUTOINST*/ // Outputs - .dout (io_packet[2*N-1:0]), // Templated + .dout (io_packet[2*NMIO-1:0]), // Templated .access_out (io_access), // Templated .wait_out (fifo_wait), // Templated // Inputs @@ -142,10 +142,10 @@ module mtx (/*AUTOARG*/ //# FAST IO (DDR) //######################################## - mtx_io #(.N(N)) + mtx_io #(.NMIO(NMIO)) mtx_io (/*AUTOINST*/ // Outputs - .tx_packet (tx_packet[N-1:0]), + .tx_packet (tx_packet[NMIO-1:0]), .tx_access (tx_access), .io_wait (io_wait), // Inputs @@ -155,7 +155,7 @@ module mtx (/*AUTOARG*/ .lsbfirst (lsbfirst), .tx_wait (tx_wait), .io_access (io_access), - .io_packet (io_packet[2*N-1:0])); + .io_packet (io_packet[2*NMIO-1:0])); endmodule // mtx // Local Variables: diff --git a/src/mio/hdl/mtx_io.v b/src/mio/hdl/mtx_io.v index 58331aa..a391d80 100644 --- a/src/mio/hdl/mtx_io.v +++ b/src/mio/hdl/mtx_io.v @@ -13,30 +13,34 @@ module mtx_io (/*AUTOARG*/ //##################################################################### //parameters - parameter N = 16; + parameter NMIO = 16; //reset, clk, cfg - input nreset; // async active low reset - input io_clk; // clock from divider - input ddr_mode; // send data as ddr - input lsbfirst; // send data lsbfirst + input nreset; // async active low reset + input io_clk; // clock from divider + input ddr_mode; // send data as ddr + input lsbfirst; // send data lsbfirst //IO interface - output [N-1:0] tx_packet; // data for IO - output tx_access; // access signal for IO - input tx_wait; // IO wait signals + output [NMIO-1:0] tx_packet; // data for IO + output tx_access; // access signal for IO + input tx_wait; // IO wait signals //Core side - input io_access; // valid packet - input [2*N-1:0] io_packet; // packet - output io_wait; // pushback to serializer in sdr mode + input io_access; // valid packet + input [2*NMIO-1:0] io_packet; // packet + output io_wait; // pushback to serializer in sdr mode + + //##################################################################### + //# BODYINTER + //##################################################################### //regs - reg tx_access; - wire [N-1:0] tx_packet_ddr; - reg [N-1:0] tx_packet_sdr; - reg byte0_sel; - wire [2*N-1:0] ddr_data; + reg tx_access; + wire [NMIO-1:0] tx_packet_ddr; + reg [NMIO-1:0] tx_packet_sdr; + reg byte0_sel; + wire [2*NMIO-1:0] ddr_data; //######################################## //# RESET @@ -64,8 +68,8 @@ module mtx_io (/*AUTOARG*/ // sampling data for sdr always @ (posedge io_clk) if(io_access) - tx_packet_sdr[N-1:0] <= byte0_sel ? io_packet[N-1:0] : - io_packet[2*N-1:N]; + tx_packet_sdr[NMIO-1:0] <= byte0_sel ? io_packet[NMIO-1:0] : + io_packet[2*NMIO-1:NMIO]; //select 2nd byte (stall on this signal) always @ (posedge io_clk) @@ -82,20 +86,20 @@ module mtx_io (/*AUTOARG*/ //######################################## // shuffle bits when in msb mode - assign ddr_data[2*N-1:0] = (~lsbfirst & ddr_mode) ? {io_packet[N-1:0], - io_packet[2*N-1:N]} : - io_packet[2*N-1:0]; - oh_oddr#(.DW(N)) - data_oddr (.out (tx_packet_ddr[N-1:0]), + assign ddr_data[2*NMIO-1:0] = (~lsbfirst & ddr_mode) ? {io_packet[NMIO-1:0], + io_packet[2*NMIO-1:NMIO]} : + io_packet[2*NMIO-1:0]; + oh_oddr#(.DW(NMIO)) + data_oddr (.out (tx_packet_ddr[NMIO-1:0]), .clk (io_clk), .ce (1'b1), - .din1 (ddr_data[N-1:0]), - .din2 (ddr_data[2*N-1:N]) + .din1 (ddr_data[NMIO-1:0]), + .din2 (ddr_data[2*NMIO-1:NMIO]) ); //select between ddr/sdr data - assign tx_packet[N-1:0] = ddr_mode ? tx_packet_ddr[N-1:0] : - tx_packet_sdr[N-1:0]; + assign tx_packet[NMIO-1:0] = ddr_mode ? tx_packet_ddr[NMIO-1:0] : + tx_packet_sdr[NMIO-1:0]; endmodule // mtx_io // Local Variables: