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Changing parameter back to NMIO

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- While N is a nice generic parameter, when integrating with a lot of other modules, it was becoming too confusing. The MIO already has three parameters: MPW, PW, and MIO. Important to keep them apart when integrating at the chip level.
This commit is contained in:
Andreas Olofsson 2016-03-25 15:35:48 -04:00
parent 4b87fdae34
commit e5665a5bc0
8 changed files with 195 additions and 187 deletions
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74
src/mio/hdl/mio.v
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@ -12,48 +12,48 @@ module mio (/*AUTOARG*/
//##################################################################### //#####################################################################
//parameters //parameters
parameter N = 8; // Mini IO width parameter NMIO = 8; // IO width
parameter AW = 32; // address width parameter AW = 32; // address width
localparam PW = 2*AW+40; // emesh packet width localparam PW = 2*AW+40; // emesh packet width
parameter MPW = 128; // mio packet width (>PW) parameter MPW = 128; // mio packet width (>PW)
parameter DEF_CFG = 0; // Default config parameter DEF_CFG = 0; // Default config
parameter DEF_CLK = 0; // Default clock parameter DEF_CLK = 0; // Default clock
parameter TARGET = "GENERIC"; // GENERIC,XILINX,ALTERA,GENERIC,ASIC parameter TARGET = "GENERIC";// GENERIC,XILINX,ALTERA,GENERIC,ASIC
// reset, clk, config // reset, clk, config
input clk; // main core clock input clk; // main core clock
input nreset; // async active low reset input nreset; // async active low reset
// tx chip interface (to IO) // tx chip interface (to IO)
output tx_clk; // phase shited io_clk output tx_clk; // phase shited io_clk
output tx_access; // access signal for IO output tx_access; // access signal for IO
output [N-1:0] tx_packet; // packet for IO output [NMIO-1:0] tx_packet; // packet for IO
input tx_wait; // pushback from IO input tx_wait; // pushback from IO
// rx chip interface (from IO) // rx chip interface (from IO)
input rx_clk; // rx clock input rx_clk; // rx clock
input rx_access; // rx access input rx_access; // rx access
input [N-1:0] rx_packet; // rx packet input [NMIO-1:0] rx_packet; // rx packet
output rx_wait; // pushback from IO output rx_wait; // pushback from IO
// core emesh interface // core emesh interface
input access_in; // access for tx input access_in; // access for tx
input [PW-1:0] packet_in; // access for tx input [PW-1:0] packet_in; // access for tx
output wait_out; // access from tx fifo output wait_out; // access from tx fifo
output access_out; // access from rx output access_out; // access from rx
output [PW-1:0] packet_out; // packet from rx output [PW-1:0] packet_out; // packet from rx
input wait_in; // pushback for rx fifo input wait_in; // pushback for rx fifo
// register config interface // register config interface
input reg_access_in; // config register access input reg_access_in; // config register access
input [PW-1:0] reg_packet_in; // config register packet input [PW-1:0] reg_packet_in; // config register packet
output reg_wait_out; // pushback by register read output reg_wait_out; // pushback by register read
output reg_access_out;// config readback output reg_access_out;// config readback
output [PW-1:0] reg_packet_out;// config reacback packet output [PW-1:0] reg_packet_out;// config reacback packet
input reg_wait_in; // pushback for readback input reg_wait_in; // pushback for readback
//##################################################################### //#####################################################################
//# BODY //# BODY
//##################################################################### //#####################################################################
@ -172,7 +172,7 @@ module mio (/*AUTOARG*/
*/ */
mio_dp #(.TARGET(TARGET), mio_dp #(.TARGET(TARGET),
.N(N), .NMIO(NMIO),
.PW(MPW)) .PW(MPW))
mio_dp(/*AUTOINST*/ mio_dp(/*AUTOINST*/
// Outputs // Outputs
@ -183,7 +183,7 @@ module mio (/*AUTOARG*/
.rx_prog_full (rx_prog_full), .rx_prog_full (rx_prog_full),
.rx_empty (rx_empty), .rx_empty (rx_empty),
.tx_access (tx_access), .tx_access (tx_access),
.tx_packet (tx_packet[N-1:0]), .tx_packet (tx_packet[NMIO-1:0]),
.rx_wait (rx_wait), .rx_wait (rx_wait),
.wait_out (tx_wait_io2c), // Templated .wait_out (tx_wait_io2c), // Templated
.access_out (rx_access_io2c), // Templated .access_out (rx_access_io2c), // Templated
@ -201,7 +201,7 @@ module mio (/*AUTOARG*/
.tx_wait (tx_wait), .tx_wait (tx_wait),
.rx_clk (rx_clk), .rx_clk (rx_clk),
.rx_access (rx_access), .rx_access (rx_access),
.rx_packet (rx_packet[N-1:0]), .rx_packet (rx_packet[NMIO-1:0]),
.access_in (tx_access_c2io), // Templated .access_in (tx_access_c2io), // Templated
.packet_in (tx_packet_c2io[MPW-1:0]), // Templated .packet_in (tx_packet_c2io[MPW-1:0]), // Templated
.wait_in (rx_wait_c2io)); // Templated .wait_in (rx_wait_c2io)); // Templated

70
src/mio/hdl/mio_dp.v
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@ -14,53 +14,53 @@ module mio_dp (/*AUTOARG*/
//parameters //parameters
parameter PW = 104; // data width (core) parameter PW = 104; // data width (core)
parameter N = 8; // Mini IO width parameter NMIO = 8; // Mini IO width
parameter TARGET = "GENERIC"; // GENERIC,XILINX,ALTERA,GENERIC,ASIC parameter TARGET = "GENERIC"; // GENERIC,XILINX,ALTERA,GENERIC,ASIC
// reset, clk, config // reset, clk, config
input clk; // main core clock input clk; // main core clock
input io_clk; // clock for TX input io_clk; // clock for TX
input nreset; // async active low reset input nreset; // async active low reset
input [7:0] datasize; // size of data transmitted input [7:0] datasize; // size of data transmitted
input ddr_mode; // dual data rate mode input ddr_mode; // dual data rate mode
input lsbfirst; // send data lsbfirst input lsbfirst; // send data lsbfirst
input framepol; // polarity of frame signal input framepol; // polarity of frame signal
input tx_en; // enable transmit input tx_en; // enable transmit
input rx_en; // enable receive input rx_en; // enable receive
// status // status
output tx_full; output tx_full;
output tx_prog_full; output tx_prog_full;
output tx_empty; output tx_empty;
output rx_full; output rx_full;
output rx_prog_full; output rx_prog_full;
output rx_empty; output rx_empty;
// tx interface // tx interface
output tx_access; // access signal for IO output tx_access; // access signal for IO
output [N-1:0] tx_packet; // packet for IO output [NMIO-1:0] tx_packet; // packet for IO
input tx_wait; // pushback from IO input tx_wait; // pushback from IO
// rx interface // rx interface
input rx_clk; // rx clock input rx_clk; // rx clock
input rx_access; // rx access input rx_access; // rx access
input [N-1:0] rx_packet; // rx packet input [NMIO-1:0] rx_packet; // rx packet
output rx_wait; // pushback from IO output rx_wait; // pushback from IO
// core interface // core interface
input access_in; // fifo data valid input access_in; // fifo data valid
input [PW-1:0] packet_in; // fifo packet input [PW-1:0] packet_in; // fifo packet
output wait_out; // wait pushback for fifo output wait_out; // wait pushback for fifo
output access_out; // fifo data valid output access_out; // fifo data valid
output [PW-1:0] packet_out; // fifo packet output [PW-1:0] packet_out; // fifo packet
input wait_in; // wait pushback for fifo input wait_in; // wait pushback for fifo
/*AUTOOUTPUT*/ /*AUTOOUTPUT*/
/*AUTOINPUT*/ /*AUTOINPUT*/
/*AUTOWIRE*/ /*AUTOWIRE*/
mtx #(.N(N), mtx #(.NMIO(NMIO),
.PW(PW)) .PW(PW))
mtx (/*AUTOINST*/ mtx (/*AUTOINST*/
// Outputs // Outputs
@ -69,7 +69,7 @@ module mio_dp (/*AUTOARG*/
.tx_prog_full (tx_prog_full), .tx_prog_full (tx_prog_full),
.wait_out (wait_out), .wait_out (wait_out),
.tx_access (tx_access), .tx_access (tx_access),
.tx_packet (tx_packet[N-1:0]), .tx_packet (tx_packet[NMIO-1:0]),
// Inputs // Inputs
.clk (clk), .clk (clk),
.io_clk (io_clk), .io_clk (io_clk),
@ -82,7 +82,7 @@ module mio_dp (/*AUTOARG*/
.packet_in (packet_in[PW-1:0]), .packet_in (packet_in[PW-1:0]),
.tx_wait (tx_wait)); .tx_wait (tx_wait));
mrx #(.N(N), mrx #(.NMIO(NMIO),
.PW(PW)) .PW(PW))
mrx (/*AUTOINST*/ mrx (/*AUTOINST*/
// Outputs // Outputs
@ -101,7 +101,7 @@ module mio_dp (/*AUTOARG*/
.framepol (framepol), .framepol (framepol),
.rx_clk (rx_clk), .rx_clk (rx_clk),
.rx_access (rx_access), .rx_access (rx_access),
.rx_packet (rx_packet[N-1:0]), .rx_packet (rx_packet[NMIO-1:0]),
.wait_in (wait_in)); .wait_in (wait_in));
endmodule // mio_dp endmodule // mio_dp

2
src/mio/hdl/mio_if.v
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@ -16,7 +16,7 @@ module mio_if (/*AUTOARG*/
//parameters //parameters
parameter AW = 32; // address width parameter AW = 32; // address width
parameter PW = 2*AW +40; // emesh packet width parameter PW = 2*AW +40; // emesh packet width
parameter MPW = PW+8; // mio packet width parameter MPW = 128; // mio packet width (> PW)
// reset, clk, config // reset, clk, config
input clk; // main core clock input clk; // main core clock

46
src/mio/hdl/mrx.v
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@ -13,33 +13,33 @@ module mrx (/*AUTOARG*/
//parameters //parameters
parameter PW = 104; // data width (core) parameter PW = 104; // data width (core)
parameter N = 8; // IO data width parameter NMIO = 8; // IO data width
parameter FIFO_DEPTH = 32; // fifo depth parameter FIFO_DEPTH = 32; // fifo depth
parameter TARGET = "GENERIC"; // GENERIC,XILINX,ALTERA,GENERIC,ASIC parameter TARGET = "GENERIC"; // GENERIC,XILINX,ALTERA,GENERIC,ASIC
//reset, clk, cfg //reset, clk, cfg
input clk; // main core clock input clk; // main core clock
input nreset; // async active low reset input nreset; // async active low reset
input [7:0] datasize; // size of data transmitted (in bytes, 0=1 byte) input [7:0] datasize; // size of data transmitted (in bytes, 0=1 byte)
input ddr_mode; input ddr_mode;
input lsbfirst; input lsbfirst;
input framepol; input framepol;
//status //status
output rx_empty; // rx fifo is empty output rx_empty; // rx fifo is empty
output rx_full; // rx fifo is full (should never happen!) output rx_full; // rx fifo is full (should never happen!)
output rx_prog_full;// rx is getting full (stop sending!) output rx_prog_full;// rx is getting full (stop sending!)
//IO interface //IO interface
input rx_clk; // clock from IO input rx_clk; // clock from IO
input rx_access; // access signal for IO input rx_access; // access signal for IO
input [N-1:0] rx_packet; // packet from IO input [NMIO-1:0] rx_packet; // packet from IO
output rx_wait; // pushback for IO output rx_wait; // pushback for IO
// data // data
output access_out; // fifo data valid output access_out; // fifo data valid
output [PW-1:0] packet_out; // fifo packet output [PW-1:0] packet_out; // fifo packet
input wait_in; // wait pushback for fifo input wait_in; // wait pushback for fifo
//##################################################################### //#####################################################################
//# BODY //# BODY
@ -53,7 +53,7 @@ module mrx (/*AUTOARG*/
wire fifo_access; // From mrx_protocol of mrx_protocol.v wire fifo_access; // From mrx_protocol of mrx_protocol.v
wire [PW-1:0] fifo_packet; // From mrx_protocol of mrx_protocol.v wire [PW-1:0] fifo_packet; // From mrx_protocol of mrx_protocol.v
wire io_access; // From mrx_io of mrx_io.v wire io_access; // From mrx_io of mrx_io.v
wire [2*N-1:0] io_packet; // From mrx_io of mrx_io.v wire [2*NMIO-1:0] io_packet; // From mrx_io of mrx_io.v
// End of automatics // End of automatics
@ -104,7 +104,7 @@ module mrx (/*AUTOARG*/
//######################################## //########################################
mrx_protocol #(.PW(PW), mrx_protocol #(.PW(PW),
.N(N)) .NMIO(NMIO))
mrx_protocol (/*AUTOINST*/ mrx_protocol (/*AUTOINST*/
// Outputs // Outputs
.fifo_access (fifo_access), .fifo_access (fifo_access),
@ -115,25 +115,25 @@ module mrx (/*AUTOARG*/
.datasize (datasize[7:0]), .datasize (datasize[7:0]),
.lsbfirst (lsbfirst), .lsbfirst (lsbfirst),
.io_access (io_access), .io_access (io_access),
.io_packet (io_packet[2*N-1:0])); .io_packet (io_packet[2*NMIO-1:0]));
//######################################## //########################################
//# FAST IO (DDR) //# FAST IO (DDR)
//######################################## //########################################
mrx_io #(.N(N)) mrx_io #(.NMIO(NMIO))
mrx_io ( mrx_io (
/*AUTOINST*/ /*AUTOINST*/
// Outputs // Outputs
.io_access (io_access), .io_access (io_access),
.io_packet (io_packet[2*N-1:0]), .io_packet (io_packet[2*NMIO-1:0]),
// Inputs // Inputs
.nreset (nreset), .nreset (nreset),
.rx_clk (rx_clk), .rx_clk (rx_clk),
.ddr_mode (ddr_mode), .ddr_mode (ddr_mode),
.lsbfirst (lsbfirst), .lsbfirst (lsbfirst),
.framepol (framepol), .framepol (framepol),
.rx_packet (rx_packet[N-1:0]), .rx_packet (rx_packet[NMIO-1:0]),
.rx_access (rx_access)); .rx_access (rx_access));
endmodule // ctx endmodule // ctx

54
src/mio/hdl/mrx_io.v
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@ -13,28 +13,32 @@ module mrx_io (/*AUTOARG*/
//##################################################################### //#####################################################################
//parameters //parameters
parameter N = 16; parameter NMIO = 16;
//RESET //RESET
input nreset; // async active low reset input nreset; // async active low reset
input rx_clk; // clock for IO input rx_clk; // clock for IO
input ddr_mode; // select between sdr/ddr data input ddr_mode; // select between sdr/ddr data
input lsbfirst; // shufle data in msbfirst mode input lsbfirst; // shufle data in msbfirst mode
input framepol; // frame polarity input framepol; // frame polarity
//IO interface //IO interface
input [N-1:0] rx_packet; // data for IO input [NMIO-1:0] rx_packet; // data for IO
input rx_access; // access signal for IO input rx_access; // access signal for IO
//FIFO interface (core side) //FIFO interface (core side)
output io_access; // fifo packet valid output io_access; // fifo packet valid
output [2*N-1:0] io_packet; // fifo packet output [2*NMIO-1:0] io_packet; // fifo packet
//#####################################################################
//# BODY
//#####################################################################
//regs //regs
reg io_access; reg io_access;
wire [2*N-1:0] ddr_data; wire [2*NMIO-1:0] ddr_data;
reg [2*N-1:0] sdr_data; reg [2*NMIO-1:0] sdr_data;
reg byte0_sel; reg byte0_sel;
//######################################## //########################################
//# CLOCK, RESET //# CLOCK, RESET
@ -66,12 +70,12 @@ module mrx_io (/*AUTOARG*/
//# DATA (DDR) //# DATA (DDR)
//######################################## //########################################
oh_iddr #(.DW(N)) oh_iddr #(.DW(NMIO))
data_iddr(.q1 (ddr_data[N-1:0]), data_iddr(.q1 (ddr_data[NMIO-1:0]),
.q2 (ddr_data[2*N-1:N]), .q2 (ddr_data[2*NMIO-1:NMIO]),
.clk (rx_clk), .clk (rx_clk),
.ce (rx_frame), .ce (rx_frame),
.din (rx_packet[N-1:0]) .din (rx_packet[NMIO-1:0])
); );
//######################################## //########################################
//# DATA (SDR) //# DATA (SDR)
@ -86,18 +90,18 @@ module mrx_io (/*AUTOARG*/
always @ (posedge rx_clk) always @ (posedge rx_clk)
if(byte0_sel) if(byte0_sel)
sdr_data[N-1:0] <= rx_packet[N-1:0]; sdr_data[NMIO-1:0] <= rx_packet[NMIO-1:0];
else else
sdr_data[2*N-1:N] <= rx_packet[N-1:0]; sdr_data[2*NMIO-1:NMIO] <= rx_packet[NMIO-1:0];
//######################################## //########################################
//# HANDL DDR/SDR //# HANDL DDR/SDR
//######################################## //########################################
assign io_packet[2*N-1:0] = ~ddr_mode ? sdr_data[2*N-1:0] : assign io_packet[2*NMIO-1:0] = ~ddr_mode ? sdr_data[2*NMIO-1:0] :
ddr_mode & ~lsbfirst ? {ddr_data[N-1:0], ddr_mode & ~lsbfirst ? {ddr_data[NMIO-1:0],
ddr_data[2*N-1:N]} : ddr_data[2*NMIO-1:NMIO]} :
ddr_data[2*N-1:0]; ddr_data[2*NMIO-1:0];
endmodule // mrx_io endmodule // mrx_io

28
src/mio/hdl/mrx_protocol.v
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@ -10,25 +10,25 @@ module mrx_protocol (/*AUTOARG*/
//##################################################################### //#####################################################################
//parameters //parameters
parameter PW = 104; // packet width (core) parameter PW = 104; // packet width (core)
parameter N = 16; // io packet width parameter NMIO = 8; // io packet width
localparam CW = $clog2(2*PW/N); // transfer count width localparam CW = $clog2(2*PW/NMIO); // transfer count width
//clock and reset //clock and reset
input rx_clk; // rx clock input rx_clk; // rx clock
input nreset; // async active low reset input nreset; // async active low reset
//config //config
input [7:0] datasize; // dynamic width of output data input [7:0] datasize; // dynamic width of output data
input lsbfirst; input lsbfirst;
//16 bit interface //16 bit interface
input io_access; // access signal from IO input io_access; // access signal from IO
input [2*N-1:0] io_packet; // data from IO input [2*NMIO-1:0] io_packet; // data from IO
//wide input interface //wide input interface
output fifo_access; // access for fifo output fifo_access; // access for fifo
output [PW-1:0] fifo_packet; // packet for fifo output [PW-1:0] fifo_packet; // packet for fifo
//##################################################################### //#####################################################################
//# BODY //# BODY
@ -78,13 +78,13 @@ module mrx_protocol (/*AUTOARG*/
//########################## //##########################
oh_ser2par #(.PW(PW), oh_ser2par #(.PW(PW),
.SW(2*N)) .SW(2*NMIO))
ser2par (// Outputs ser2par (// Outputs
.dout (fifo_packet[PW-1:0]), .dout (fifo_packet[PW-1:0]),
// Inputs // Inputs
.clk (rx_clk), .clk (rx_clk),
.din (io_packet), .din (io_packet[2*NMIO-1:0]),
.lsbfirst (lsbfirst), .lsbfirst (lsbfirst),
.shift (shift) .shift (shift)
); );

50
src/mio/hdl/mtx.v
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@ -13,34 +13,34 @@ module mtx (/*AUTOARG*/
//parameters //parameters
parameter PW = 104; // data width (core) parameter PW = 104; // data width (core)
parameter N = 16; // IO data width parameter NMIO = 8; // IO data width
parameter FIFO_DEPTH = 32; // fifo depth parameter FIFO_DEPTH = 32; // fifo depth
parameter TARGET = "GENERIC"; // GENERIC,XILINX,ALTERA,GENERIC,ASIC parameter TARGET = "GENERIC"; // GENERIC,XILINX,ALTERA,GENERIC,ASIC
localparam CW = $clog2(2*PW/N); // transfer count width localparam CW = $clog2(2*PW/NMIO); // transfer count width
//reset, clk, cfg //reset, clk, cfg
input clk; // main core clock input clk; // main core clock
input io_clk; // clock for tx logic input io_clk; // clock for tx logic
input nreset; // async active low reset input nreset; // async active low reset
input tx_en; // transmit enable input tx_en; // transmit enable
input [7:0] datasize; // size of data transmitted/received input [7:0] datasize; // size of data transmitted/received
input ddr_mode; // configure mio in ddr mode input ddr_mode; // configure mio in ddr mode
input lsbfirst; // send bits lsb first input lsbfirst; // send bits lsb first
//status //status
output tx_empty; // tx fifo is empty output tx_empty; // tx fifo is empty
output tx_full; // tx fifo is full (should never happen!) output tx_full; // tx fifo is full (should never happen!)
output tx_prog_full;// tx is getting full (stop sending!) output tx_prog_full;// tx is getting full (stop sending!)
// data to transmit // data to transmit
input access_in; // fifo data valid input access_in; // fifo data valid
input [PW-1:0] packet_in; // fifo packet input [PW-1:0] packet_in; // fifo packet
output wait_out; // wait pushback for fifo output wait_out; // wait pushback for fifo
//IO interface (90 deg clock supplied outside this block) //IO interface (90 deg clock supplied outside this block)
output tx_access; // access signal for IO output tx_access; // access signal for IO
output [N-1:0] tx_packet; // packet for IO output [NMIO-1:0] tx_packet; // packet for IO
input tx_wait; // pushback from IO input tx_wait; // pushback from IO
//##################################################################### //#####################################################################
//# BODY //# BODY
@ -54,7 +54,7 @@ module mtx (/*AUTOARG*/
wire [PW-1:0] fifo_packet; // From fifo of oh_fifo_cdc.v wire [PW-1:0] fifo_packet; // From fifo of oh_fifo_cdc.v
wire fifo_wait; // From par2ser of oh_par2ser.v wire fifo_wait; // From par2ser of oh_par2ser.v
wire io_access; // From par2ser of oh_par2ser.v wire io_access; // From par2ser of oh_par2ser.v
wire [2*N-1:0] io_packet; // From par2ser of oh_par2ser.v wire [2*NMIO-1:0] io_packet; // From par2ser of oh_par2ser.v
wire io_wait; // From mtx_io of mtx_io.v wire io_wait; // From mtx_io of mtx_io.v
// End of automatics // End of automatics
@ -104,7 +104,7 @@ module mtx (/*AUTOARG*/
//######################################## //########################################
/*oh_par2ser AUTO_TEMPLATE (// outputs /*oh_par2ser AUTO_TEMPLATE (// outputs
.dout (io_packet[2*N-1:0]), .dout (io_packet[2*NMIO-1:0]),
.access_out (io_access), .access_out (io_access),
.wait_out (fifo_wait), .wait_out (fifo_wait),
// inputs // inputs
@ -121,10 +121,10 @@ module mtx (/*AUTOARG*/
*/ */
oh_par2ser #(.PW(PW), oh_par2ser #(.PW(PW),
.SW(2*N)) .SW(2*NMIO))
par2ser (/*AUTOINST*/ par2ser (/*AUTOINST*/
// Outputs // Outputs
.dout (io_packet[2*N-1:0]), // Templated .dout (io_packet[2*NMIO-1:0]), // Templated
.access_out (io_access), // Templated .access_out (io_access), // Templated
.wait_out (fifo_wait), // Templated .wait_out (fifo_wait), // Templated
// Inputs // Inputs
@ -142,10 +142,10 @@ module mtx (/*AUTOARG*/
//# FAST IO (DDR) //# FAST IO (DDR)
//######################################## //########################################
mtx_io #(.N(N)) mtx_io #(.NMIO(NMIO))
mtx_io (/*AUTOINST*/ mtx_io (/*AUTOINST*/
// Outputs // Outputs
.tx_packet (tx_packet[N-1:0]), .tx_packet (tx_packet[NMIO-1:0]),
.tx_access (tx_access), .tx_access (tx_access),
.io_wait (io_wait), .io_wait (io_wait),
// Inputs // Inputs
@ -155,7 +155,7 @@ module mtx (/*AUTOARG*/
.lsbfirst (lsbfirst), .lsbfirst (lsbfirst),
.tx_wait (tx_wait), .tx_wait (tx_wait),
.io_access (io_access), .io_access (io_access),
.io_packet (io_packet[2*N-1:0])); .io_packet (io_packet[2*NMIO-1:0]));
endmodule // mtx endmodule // mtx
// Local Variables: // Local Variables:

58
src/mio/hdl/mtx_io.v
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@ -13,30 +13,34 @@ module mtx_io (/*AUTOARG*/
//##################################################################### //#####################################################################
//parameters //parameters
parameter N = 16; parameter NMIO = 16;
//reset, clk, cfg //reset, clk, cfg
input nreset; // async active low reset input nreset; // async active low reset
input io_clk; // clock from divider input io_clk; // clock from divider
input ddr_mode; // send data as ddr input ddr_mode; // send data as ddr
input lsbfirst; // send data lsbfirst input lsbfirst; // send data lsbfirst
//IO interface //IO interface
output [N-1:0] tx_packet; // data for IO output [NMIO-1:0] tx_packet; // data for IO
output tx_access; // access signal for IO output tx_access; // access signal for IO
input tx_wait; // IO wait signals input tx_wait; // IO wait signals
//Core side //Core side
input io_access; // valid packet input io_access; // valid packet
input [2*N-1:0] io_packet; // packet input [2*NMIO-1:0] io_packet; // packet
output io_wait; // pushback to serializer in sdr mode output io_wait; // pushback to serializer in sdr mode
//#####################################################################
//# BODYINTER
//#####################################################################
//regs //regs
reg tx_access; reg tx_access;
wire [N-1:0] tx_packet_ddr; wire [NMIO-1:0] tx_packet_ddr;
reg [N-1:0] tx_packet_sdr; reg [NMIO-1:0] tx_packet_sdr;
reg byte0_sel; reg byte0_sel;
wire [2*N-1:0] ddr_data; wire [2*NMIO-1:0] ddr_data;
//######################################## //########################################
//# RESET //# RESET
@ -64,8 +68,8 @@ module mtx_io (/*AUTOARG*/
// sampling data for sdr // sampling data for sdr
always @ (posedge io_clk) always @ (posedge io_clk)
if(io_access) if(io_access)
tx_packet_sdr[N-1:0] <= byte0_sel ? io_packet[N-1:0] : tx_packet_sdr[NMIO-1:0] <= byte0_sel ? io_packet[NMIO-1:0] :
io_packet[2*N-1:N]; io_packet[2*NMIO-1:NMIO];
//select 2nd byte (stall on this signal) //select 2nd byte (stall on this signal)
always @ (posedge io_clk) always @ (posedge io_clk)
@ -82,20 +86,20 @@ module mtx_io (/*AUTOARG*/
//######################################## //########################################
// shuffle bits when in msb mode // shuffle bits when in msb mode
assign ddr_data[2*N-1:0] = (~lsbfirst & ddr_mode) ? {io_packet[N-1:0], assign ddr_data[2*NMIO-1:0] = (~lsbfirst & ddr_mode) ? {io_packet[NMIO-1:0],
io_packet[2*N-1:N]} : io_packet[2*NMIO-1:NMIO]} :
io_packet[2*N-1:0]; io_packet[2*NMIO-1:0];
oh_oddr#(.DW(N)) oh_oddr#(.DW(NMIO))
data_oddr (.out (tx_packet_ddr[N-1:0]), data_oddr (.out (tx_packet_ddr[NMIO-1:0]),
.clk (io_clk), .clk (io_clk),
.ce (1'b1), .ce (1'b1),
.din1 (ddr_data[N-1:0]), .din1 (ddr_data[NMIO-1:0]),
.din2 (ddr_data[2*N-1:N]) .din2 (ddr_data[2*NMIO-1:NMIO])
); );
//select between ddr/sdr data //select between ddr/sdr data
assign tx_packet[N-1:0] = ddr_mode ? tx_packet_ddr[N-1:0] : assign tx_packet[NMIO-1:0] = ddr_mode ? tx_packet_ddr[NMIO-1:0] :
tx_packet_sdr[N-1:0]; tx_packet_sdr[NMIO-1:0];
endmodule // mtx_io endmodule // mtx_io
// Local Variables: // Local Variables: