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Adding edge align circuit

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This commit is contained in:
Andreas Olofsson 2015-11-14 22:41:19 -05:00
parent 75710f25b7
commit e70c51670c
1 changed files with 47 additions and 0 deletions
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common/hdl/edgealign.v Normal file
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/* Detects the common aligned positive edge for a
* slow/fast clocks
*
* NOTE: Assumes clocks are aligned and synchronous!
*
* ___________ ___________
* __/ \___________/ \ SLOWCLK
* __ __ __ __ __ __
* _/ \__/ \__/ \__/ \__/ \__/ \__/ FASTCLK
* ___________ _________
* __/ \___________/ CLK45
* ___________ ___
* ________/ \___________/ CLK135
*
* ____ ______
* \__________________/ \________ FIRSTEDGE
*
*/
module edgealign (/*AUTOARG*/
// Outputs
firstedge,
// Inputs
fastclk, slowclk
);
input fastclk;
input slowclk;
output firstedge;
reg clk45;
reg clk135;
reg firstedge;
always @ (negedge fastclk)
begin
clk45 <= slowclk;
clk135 <= clk45;
firstedge <= ~clk45 & ~clk135;
end
//TODO: parametrized based on 1/N ratios?
endmodule // edgealign