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Adding etx/erx core modules
-Single clock domain -Super-light... -Need to be able to remove internal feature as well -(MMU/DMA should be optional but on by default..)
This commit is contained in:
Andreas Olofsson
parent
fa374e666a
commit
eaadfc6465
365
elink/hdl/erx_core.v
Normal file
365
elink/hdl/erx_core.v
Normal file
@ -0,0 +1,365 @@
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module erx_core (/*AUTOARG*/
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// Outputs
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rx_rd_wait, rx_wr_wait, rxrd_fifo_access, rxrd_fifo_packet,
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rxrr_fifo_access, rxrr_fifo_packet, rxwr_fifo_access,
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rxwr_fifo_packet, erx_cfg_wait, mailbox_full, mailbox_not_empty,
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// Inputs
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reset, clk, rx_data_par, rx_frame_par, rxrd_fifo_wait,
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rxrr_fifo_wait, rxwr_fifo_wait, erx_cfg_access, erx_cfg_packet
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);
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parameter AW = 32;
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parameter DW = 32;
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parameter PW = 104;
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parameter RFAW = 6;
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parameter ID = 12'h800;
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//clock and reset
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input reset;
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input clk;
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//IO Interface
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input [63:0] rx_data_par;
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input [7:0] rx_frame_par;
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output rx_rd_wait;
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output rx_wr_wait;
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//FIFO Access
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output rxrd_fifo_access;
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output [PW-1:0] rxrd_fifo_packet;
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input rxrd_fifo_wait;
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output rxrr_fifo_access;
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output [PW-1:0] rxrr_fifo_packet;
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input rxrr_fifo_wait;
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output rxwr_fifo_access;
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output [PW-1:0] rxwr_fifo_packet;
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input rxwr_fifo_wait;
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//register interface
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input erx_cfg_access;
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input [PW-1:0] erx_cfg_packet;
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output erx_cfg_wait;
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//mailbox outputs
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output mailbox_full; //need to sync to sys_clk
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output mailbox_not_empty; //need to sync to sys_clk
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/*AUTOINPUT*/
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/*AUTOOUTPUT*/
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//regs
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wire [8:0] gpio_datain; // To erx_cfg of erx_cfg.v
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wire [15:0] rx_status;
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wire rxwr_fifo_full;
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wire rxrr_fifo_full;
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wire rxrd_fifo_full;
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wire rxrd_empty;
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wire rxwr_empty;
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wire rxrr_empty;
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wire [103:0] edma_packet; // From edma of edma.v, ...
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/**************************************************************/
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/*ELINK PROTOCOL LOGIC */
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/**************************************************************/
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defparam erx_protocol.ID=ID;
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erx_protocol erx_protocol (/*AUTOINST*/
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// Outputs
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.erx_access (erx_access),
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.erx_packet (erx_packet[PW-1:0]),
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.remap_bypass (remap_bypass),
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// Inputs
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.reset (reset),
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.rx_enable (rx_enable),
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.clk (clk),
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.rx_frame_par (rx_frame_par[7:0]),
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.rx_data_par (rx_data_par[63:0]));
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/**************************************************************/
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/*ADDRESS REMPAPPING */
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/**************************************************************/
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/*erx_remap AUTO_TEMPLATE (
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.emesh_\(.*\)_out (emesh_remap_\1[]),
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//Inputs
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.emesh_\(.*\)_in (erx_\1[]),
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.mmu_en (ecfg_rx_mmu_enable),
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.emesh_packet_hi_out (),
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);
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*/
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defparam erx_remap.ID = ID;
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erx_remap erx_remap (/*AUTOINST*/
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// Outputs
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.emesh_access_out(emesh_remap_access), // Templated
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.emesh_packet_out(emesh_remap_packet[PW-1:0]), // Templated
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// Inputs
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.clk (clk),
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.reset (reset),
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.emesh_access_in(erx_access), // Templated
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.emesh_packet_in(erx_packet[PW-1:0]), // Templated
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.remap_mode (remap_mode[1:0]),
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.remap_sel (remap_sel[11:0]),
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.remap_pattern (remap_pattern[11:0]),
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.remap_base (remap_base[31:0]),
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.remap_bypass (remap_bypass),
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.rx_rd_wait (rx_rd_wait),
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.rx_wr_wait (rx_wr_wait));
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/************************************************************/
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/*ELINK MEMORY MANAGEMENT UNIT */
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/************************************************************/
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/*emmu AUTO_TEMPLATE (
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.emesh_\(.*\)_out (emmu_\1[]),
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//Inputs
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.emesh_\(.*\)_in (emesh_remap_\1[]),
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.mmu_en (mmu_enable),
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.rd_clk (clk),
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.wr_clk (clk),
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.mi_dout (mi_mmu_dout[DW-1:0]),
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.emesh_packet_hi_out (),
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.mmu_bp (remap_bypass),
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.mi_en (mi_mmu_en),
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.emesh_rd_wait (rx_rd_wait),
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.emesh_wr_wait (rx_wr_wait),
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);
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*/
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emmu erx_mmu (
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/*AUTOINST*/
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// Outputs
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.mi_dout (mi_mmu_dout[DW-1:0]), // Templated
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.emesh_access_out (emmu_access), // Templated
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.emesh_packet_out (emmu_packet[PW-1:0]), // Templated
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.emesh_packet_hi_out (), // Templated
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// Inputs
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.reset (reset),
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.rd_clk (clk), // Templated
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.wr_clk (clk), // Templated
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.mmu_en (mmu_enable), // Templated
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.mmu_bp (remap_bypass), // Templated
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.mi_en (mi_mmu_en), // Templated
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.mi_we (mi_we),
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.mi_addr (mi_addr[14:0]),
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.mi_din (mi_din[DW-1:0]),
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.emesh_access_in (emesh_remap_access), // Templated
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.emesh_packet_in (emesh_remap_packet[PW-1:0]), // Templated
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.emesh_rd_wait (rx_rd_wait), // Templated
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.emesh_wr_wait (rx_wr_wait)); // Templated
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/************************************************************/
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/*EMAILBOX */
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/************************************************************/
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/*emailbox AUTO_TEMPLATE (
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.mi_en (mi_cfg_en),
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.mi_dout (mi_mailbox_dout[]),
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.wr_clk (clk),
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.rd_clk (clk),
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.emesh_access (emmu_access),
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.emesh_packet (emmu_packet[PW-1:0]),
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);
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*/
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defparam erx_mailbox.ID=ID;
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emailbox erx_mailbox(
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/*AUTOINST*/
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// Outputs
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.mi_dout (mi_mailbox_dout[63:0]), // Templated
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.mailbox_full (mailbox_full),
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.mailbox_not_empty(mailbox_not_empty),
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// Inputs
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.reset (reset),
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.wr_clk (clk), // Templated
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.rd_clk (clk), // Templated
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.emesh_access (emmu_access), // Templated
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.emesh_packet (emmu_packet[PW-1:0]), // Templated
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.mi_en (mi_cfg_en), // Templated
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.mi_we (mi_we),
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.mi_addr (mi_addr[RFAW+1:0]),
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.mi_din (mi_din[63:0]));
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/************************************************************/
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/* CONFIGURATION INTERFACE */
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/************************************************************/
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/*ecfg_if AUTO_TEMPLATE (
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.wait_in (erx_cfg_wait),
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.\(.*\)_in (erx_cfg_\1[]),
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.\(.*\)_out (ecfg_\1[]),
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.mi_dout0 ({32'b0,mi_cfg_dout[31:0]}),
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.mi_dout1 ({32'b0,mi_dma_dout[31:0]}),
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.mi_dout2 ({32'b0,mi_mmu_dout[31:0]}),
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.mi_dout3 (mi_mailbox_dout[63:0]),
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);
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*/
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defparam erx_cfgif.RX=1;
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ecfg_if erx_cfgif (/*AUTOINST*/
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// Outputs
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.mi_mmu_en (mi_mmu_en),
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.mi_dma_en (mi_dma_en),
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.mi_cfg_en (mi_cfg_en),
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.mi_we (mi_we),
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.mi_addr (mi_addr[14:0]),
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.mi_din (mi_din[63:0]),
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.access_out (ecfg_access), // Templated
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.packet_out (ecfg_packet[PW-1:0]), // Templated
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// Inputs
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.clk (clk),
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.reset (reset),
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.access_in (erx_cfg_access), // Templated
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.packet_in (erx_cfg_packet[PW-1:0]), // Templated
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.mi_dout0 ({32'b0,mi_cfg_dout[31:0]}), // Templated
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.mi_dout1 ({32'b0,mi_dma_dout[31:0]}), // Templated
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.mi_dout2 ({32'b0,mi_mmu_dout[31:0]}), // Templated
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.mi_dout3 (mi_mailbox_dout[63:0]), // Templated
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.wait_in (erx_cfg_wait)); // Templated
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/************************************************************/
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/* ERX CONFIGURATION */
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/************************************************************/
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/*erx_cfg AUTO_TEMPLATE (.mi_dout (mi_cfg_dout[DW-1:0]),
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.mi_en (mi_cfg_en),
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);
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*/
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assign rx_status[15:0] = {16'b0};
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assign gpio_datain[8:0]= {rx_frame_par[0],
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rx_data_par[7],
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rx_data_par[6],
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rx_data_par[5],
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rx_data_par[4],
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rx_data_par[3],
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rx_data_par[2],
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rx_data_par[1],
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rx_data_par[0]
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};
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erx_cfg erx_cfg (.rx_status (rx_status[15:0]),
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.timer_cfg (),
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/*AUTOINST*/
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// Outputs
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.mi_dout (mi_cfg_dout[DW-1:0]), // Templated
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.rx_enable (rx_enable),
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.mmu_enable (mmu_enable),
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.remap_mode (remap_mode[1:0]),
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.remap_base (remap_base[31:0]),
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.remap_pattern (remap_pattern[11:0]),
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.remap_sel (remap_sel[11:0]),
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// Inputs
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.reset (reset),
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.clk (clk),
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.mi_en (mi_cfg_en), // Templated
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.mi_we (mi_we),
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.mi_addr (mi_addr[14:0]),
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.mi_din (mi_din[31:0]),
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.gpio_datain (gpio_datain[8:0]));
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/************************************************************/
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/*ELINK DMA */
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/************************************************************/
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/*edma AUTO_TEMPLATE (
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.mi_en (mi_dma_en),
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.edma_access (edma_access),
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.mi_dout (mi_dma_dout[DW-1:0]),
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);
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*/
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edma erx_dma(/*AUTOINST*/
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// Outputs
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.mi_dout (mi_dma_dout[DW-1:0]), // Templated
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.edma_access (edma_access), // Templated
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.edma_packet (edma_packet[PW-1:0]),
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// Inputs
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.reset (reset),
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.clk (clk),
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.mi_en (mi_dma_en), // Templated
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.mi_we (mi_we),
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.mi_addr (mi_addr[RFAW+1:0]),
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.mi_din (mi_din[63:0]),
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.edma_wait (edma_wait));
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/************************************************************/
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/*ELINK RECEIVE DISTRIBUTOR ("DEMUX") */
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/*(figures out who RX transaction belongs to) */
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/********************1***************************************/
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/*erx_disty AUTO_TEMPLATE (
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//Inputs
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.mmu_en (ecfg_rx_mmu_enable),
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.ecfg_wait (erx_cfg_wait),
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)
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*/
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defparam erx_disty.ID = ID;
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erx_disty erx_disty (.timeout (1'b0),//TODO
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/*AUTOINST*/
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// Outputs
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.rx_rd_wait (rx_rd_wait),
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.rx_wr_wait (rx_wr_wait),
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.edma_wait (edma_wait),
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.ecfg_wait (erx_cfg_wait), // Templated
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.rxwr_fifo_access(rxwr_fifo_access),
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.rxwr_fifo_packet(rxwr_fifo_packet[PW-1:0]),
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.rxrd_fifo_access(rxrd_fifo_access),
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.rxrd_fifo_packet(rxrd_fifo_packet[PW-1:0]),
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.rxrr_fifo_access(rxrr_fifo_access),
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.rxrr_fifo_packet(rxrr_fifo_packet[PW-1:0]),
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// Inputs
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.erx_access (erx_access),
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.erx_packet (erx_packet[PW-1:0]),
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.emmu_access (emmu_access),
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.emmu_packet (emmu_packet[PW-1:0]),
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.edma_access (edma_access),
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.edma_packet (edma_packet[PW-1:0]),
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.ecfg_access (ecfg_access),
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.ecfg_packet (ecfg_packet[PW-1:0]),
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.rxwr_fifo_wait (rxwr_fifo_wait),
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.rxrd_fifo_wait (rxrd_fifo_wait),
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.rxrr_fifo_wait (rxrr_fifo_wait));
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endmodule // erx
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// Local Variables:
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// verilog-library-directories:("." "../../emmu/hdl" "../../edma/hdl" "../../memory/hdl" "../../emailbox/hdl")
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// End:
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/*
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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354
elink/hdl/etx_core.v
Normal file
354
elink/hdl/etx_core.v
Normal file
@ -0,0 +1,354 @@
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module etx_core(/*AUTOARG*/
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// Outputs
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tx_data_par, tx_frame_par, txrd_wait, txrr_wait, txwr_wait,
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etx_cfg_access, etx_cfg_packet,
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// Inputs
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reset, clk, tx_rd_wait, tx_wr_wait, txrd_access, txrd_packet,
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txrr_access, txrr_packet, txwr_access, txwr_packet, etx_cfg_wait
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);
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parameter AW = 32;
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parameter DW = 32;
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parameter PW = 104;
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parameter RFAW = 6;
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parameter ID = 12'h000;
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//Clocks,reset,config
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input reset;
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input clk;
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//IO interface
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output [63:0] tx_data_par;
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output [7:0] tx_frame_par;
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input tx_rd_wait;
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input tx_wr_wait;
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//TXRD
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input txrd_access;
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input [PW-1:0] txrd_packet;
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output txrd_wait;
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//TXRR
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input txrr_access;
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input [PW-1:0] txrr_packet;
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output txrr_wait;
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//TXWR
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input txwr_access;
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input [PW-1:0] txwr_packet;
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output txwr_wait;
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//Configuration Interface (for ERX)
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output etx_cfg_access;
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output [PW-1:0] etx_cfg_packet;
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input etx_cfg_wait;
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//for status?
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wire[15:0] tx_status;
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/*AUTOOUTPUT*/
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/*AUTOINPUT*/
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [3:0] ctrlmode; // From etx_cfg of etx_cfg.v
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wire ctrlmode_bypass; // From etx_cfg of etx_cfg.v
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wire edma_access; // From etx_dma of edma.v
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wire [PW-1:0] edma_packet; // From etx_dma of edma.v
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wire edma_wait; // From etx_arbiter of etx_arbiter.v
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wire emmu_access; // From etx_mmu of emmu.v
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wire [PW-1:0] emmu_packet; // From etx_mmu of emmu.v
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wire etx_access; // From etx_arbiter of etx_arbiter.v
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wire [PW-1:0] etx_packet; // From etx_arbiter of etx_arbiter.v
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wire etx_rd_wait; // From etx_protocol of etx_protocol.v
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wire etx_remap_access; // From etx_remap of etx_remap.v
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wire [PW-1:0] etx_remap_packet; // From etx_remap of etx_remap.v
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wire etx_rr; // From etx_arbiter of etx_arbiter.v
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wire etx_wr_wait; // From etx_protocol of etx_protocol.v
|
||||
wire [8:0] gpio_data; // From etx_cfg of etx_cfg.v
|
||||
wire gpio_enable; // From etx_cfg of etx_cfg.v
|
||||
wire [14:0] mi_addr; // From etx_cfgif of ecfg_if.v
|
||||
wire [DW-1:0] mi_cfg_dout; // From etx_cfg of etx_cfg.v
|
||||
wire mi_cfg_en; // From etx_cfgif of ecfg_if.v
|
||||
wire [63:0] mi_din; // From etx_cfgif of ecfg_if.v
|
||||
wire [DW-1:0] mi_dma_dout; // From etx_dma of edma.v
|
||||
wire mi_dma_en; // From etx_cfgif of ecfg_if.v
|
||||
wire [DW-1:0] mi_mmu_dout; // From etx_mmu of emmu.v
|
||||
wire mi_mmu_en; // From etx_cfgif of ecfg_if.v
|
||||
wire mi_we; // From etx_cfgif of ecfg_if.v
|
||||
wire mmu_enable; // From etx_cfg of etx_cfg.v
|
||||
wire remap_enable; // From etx_cfg of etx_cfg.v
|
||||
wire tx_enable; // From etx_cfg of etx_cfg.v
|
||||
// End of automatics
|
||||
|
||||
/************************************************************/
|
||||
/*EDMA ("4th channel") */
|
||||
/************************************************************/
|
||||
|
||||
|
||||
/*edma AUTO_TEMPLATE (
|
||||
.mi_en (mi_dma_en),
|
||||
.edma_access (edma_access),
|
||||
.mi_dout (mi_dma_dout[DW-1:0]),
|
||||
.edma_access (edma_access),
|
||||
.edma_write (edma_packet[1]),
|
||||
.edma_datamode (edma_packet[3:2]),
|
||||
.edma_ctrlmode (edma_packet[7:4]),
|
||||
.edma_dstaddr (edma_packet[39:8]),
|
||||
.edma_data (edma_packet[71:40]),
|
||||
.edma_srcaddr (edma_packet[103:72]),
|
||||
);
|
||||
*/
|
||||
|
||||
edma etx_dma (/*AUTOINST*/
|
||||
// Outputs
|
||||
.mi_dout (mi_dma_dout[DW-1:0]), // Templated
|
||||
.edma_access (edma_access), // Templated
|
||||
.edma_packet (edma_packet[PW-1:0]),
|
||||
// Inputs
|
||||
.reset (reset),
|
||||
.clk (clk),
|
||||
.mi_en (mi_dma_en), // Templated
|
||||
.mi_we (mi_we),
|
||||
.mi_addr (mi_addr[RFAW+1:0]),
|
||||
.mi_din (mi_din[63:0]),
|
||||
.edma_wait (edma_wait));
|
||||
|
||||
/************************************************************/
|
||||
/*ELINK TRANSMIT ARBITER */
|
||||
/************************************************************/
|
||||
defparam etx_arbiter.ID=ID;
|
||||
etx_arbiter etx_arbiter (
|
||||
/*AUTOINST*/
|
||||
// Outputs
|
||||
.txwr_wait (txwr_wait),
|
||||
.txrd_wait (txrd_wait),
|
||||
.txrr_wait (txrr_wait),
|
||||
.edma_wait (edma_wait),
|
||||
.etx_access (etx_access),
|
||||
.etx_packet (etx_packet[PW-1:0]),
|
||||
.etx_rr (etx_rr),
|
||||
// Inputs
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.txwr_access (txwr_access),
|
||||
.txwr_packet (txwr_packet[PW-1:0]),
|
||||
.txrd_access (txrd_access),
|
||||
.txrd_packet (txrd_packet[PW-1:0]),
|
||||
.txrr_access (txrr_access),
|
||||
.txrr_packet (txrr_packet[PW-1:0]),
|
||||
.edma_access (edma_access),
|
||||
.edma_packet (edma_packet[PW-1:0]),
|
||||
.etx_rd_wait (etx_rd_wait),
|
||||
.etx_wr_wait (etx_wr_wait),
|
||||
.etx_cfg_wait (etx_cfg_wait),
|
||||
.ctrlmode_bypass (ctrlmode_bypass),
|
||||
.ctrlmode (ctrlmode[3:0]));
|
||||
|
||||
|
||||
/************************************************************/
|
||||
/* CONFIGURATOIN PACKET */
|
||||
/************************************************************/
|
||||
/*ecfg_if AUTO_TEMPLATE (
|
||||
.\(.*\)_in (etx_\1[]),
|
||||
.\(.*\)_out (etx_cfg_\1[]),
|
||||
.mi_dout0 ({32'b0,mi_cfg_dout[31:0]}),
|
||||
.mi_dout1 ({32'b0,mi_dma_dout[31:0]}),
|
||||
.mi_dout2 ({32'b0,mi_mmu_dout[31:0]}),
|
||||
.wait_in (etx_cfg_wait),
|
||||
);
|
||||
*/
|
||||
|
||||
defparam etx_cfgif.RX =0;
|
||||
ecfg_if etx_cfgif (.mi_dout3 (64'b0),
|
||||
/*AUTOINST*/
|
||||
// Outputs
|
||||
.mi_mmu_en (mi_mmu_en),
|
||||
.mi_dma_en (mi_dma_en),
|
||||
.mi_cfg_en (mi_cfg_en),
|
||||
.mi_we (mi_we),
|
||||
.mi_addr (mi_addr[14:0]),
|
||||
.mi_din (mi_din[63:0]),
|
||||
.access_out (etx_cfg_access), // Templated
|
||||
.packet_out (etx_cfg_packet[PW-1:0]), // Templated
|
||||
// Inputs
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.access_in (etx_access), // Templated
|
||||
.packet_in (etx_packet[PW-1:0]), // Templated
|
||||
.mi_dout0 ({32'b0,mi_cfg_dout[31:0]}), // Templated
|
||||
.mi_dout1 ({32'b0,mi_dma_dout[31:0]}), // Templated
|
||||
.mi_dout2 ({32'b0,mi_mmu_dout[31:0]}), // Templated
|
||||
.wait_in (etx_cfg_wait)); // Templated
|
||||
|
||||
/************************************************************/
|
||||
/* ETX CONFIGURATION REGISTERS */
|
||||
/************************************************************/
|
||||
/*etx_cfg AUTO_TEMPLATE (.mi_dout (mi_cfg_dout[DW-1:0]),
|
||||
.mi_en (mi_cfg_en),
|
||||
);
|
||||
*/
|
||||
|
||||
//todo: make more useufl
|
||||
assign tx_status[15:0] = 16'b0;
|
||||
/*
|
||||
|
||||
{2'b0, //15:14
|
||||
etx_rd_wait, //13
|
||||
etx_wr_wait, //12
|
||||
txrr_fifo_read, //11
|
||||
txrr_wait, //10
|
||||
txrr_access, //9
|
||||
txrd_fifo_read, //8
|
||||
txrd_wait, //7
|
||||
txrd_access, //6
|
||||
txwr_fifo_read, //5
|
||||
txwr_wait, //4
|
||||
txwr_access, //3
|
||||
1'b0, //2
|
||||
1'b0, //1
|
||||
1'b0 //0
|
||||
};
|
||||
*/
|
||||
|
||||
etx_cfg etx_cfg (
|
||||
/*AUTOINST*/
|
||||
// Outputs
|
||||
.mi_dout (mi_cfg_dout[DW-1:0]), // Templated
|
||||
.tx_enable (tx_enable),
|
||||
.mmu_enable (mmu_enable),
|
||||
.gpio_enable (gpio_enable),
|
||||
.remap_enable (remap_enable),
|
||||
.gpio_data (gpio_data[8:0]),
|
||||
.ctrlmode (ctrlmode[3:0]),
|
||||
.ctrlmode_bypass (ctrlmode_bypass),
|
||||
// Inputs
|
||||
.reset (reset),
|
||||
.clk (clk),
|
||||
.mi_en (mi_cfg_en), // Templated
|
||||
.mi_we (mi_we),
|
||||
.mi_addr (mi_addr[RFAW+1:0]),
|
||||
.mi_din (mi_din[31:0]),
|
||||
.tx_status (tx_status[15:0]));
|
||||
|
||||
/************************************************************/
|
||||
/* REMAPPING (SHIFT) DESTINATION ADDRESS */
|
||||
/************************************************************/
|
||||
/*etx_remap AUTO_TEMPLATE (
|
||||
.emesh_\(.*\)_in (etx_\1[]),
|
||||
.emesh_\(.*\)_out (etx_remap_\1[]),
|
||||
.remap_en (remap_enable),
|
||||
.remap_bypass (etx_rr),
|
||||
.emesh_wait (etx_wait),
|
||||
);
|
||||
*/
|
||||
|
||||
etx_remap etx_remap (/*AUTOINST*/
|
||||
// Outputs
|
||||
.emesh_access_out(etx_remap_access), // Templated
|
||||
.emesh_packet_out(etx_remap_packet[PW-1:0]), // Templated
|
||||
// Inputs
|
||||
.clk (clk),
|
||||
.reset (reset),
|
||||
.emesh_access_in(etx_access), // Templated
|
||||
.emesh_packet_in(etx_packet[PW-1:0]), // Templated
|
||||
.remap_en (remap_enable), // Templated
|
||||
.remap_bypass (etx_rr), // Templated
|
||||
.etx_rd_wait (etx_rd_wait),
|
||||
.etx_wr_wait (etx_wr_wait));
|
||||
|
||||
|
||||
/************************************************************/
|
||||
/* EMMU */
|
||||
/************************************************************/
|
||||
/*emmu AUTO_TEMPLATE (
|
||||
.emesh_\(.*\)_in (etx_remap_\1[]),
|
||||
.emesh_\(.*\)_out (emmu_\1[]),
|
||||
.mmu_en (mmu_enable),
|
||||
.mmu_bp (etx_rr),
|
||||
.rd_clk (clk),
|
||||
.wr_clk (clk),
|
||||
.emmu_access_out (emmu_access),
|
||||
.emmu_packet_out (emmu_packet[PW-1:0]),
|
||||
.mi_dout (mi_mmu_dout[DW-1:0]),
|
||||
.emesh_rd_wait (etx_rd_wait),
|
||||
.emesh_wr_wait (etx_wr_wait),
|
||||
.emesh_packet_hi_out (),
|
||||
.mi_en (mi_mmu_en),
|
||||
);
|
||||
*/
|
||||
|
||||
emmu etx_mmu (
|
||||
/*AUTOINST*/
|
||||
// Outputs
|
||||
.mi_dout (mi_mmu_dout[DW-1:0]), // Templated
|
||||
.emesh_access_out (emmu_access), // Templated
|
||||
.emesh_packet_out (emmu_packet[PW-1:0]), // Templated
|
||||
.emesh_packet_hi_out (), // Templated
|
||||
// Inputs
|
||||
.reset (reset),
|
||||
.rd_clk (clk), // Templated
|
||||
.wr_clk (clk), // Templated
|
||||
.mmu_en (mmu_enable), // Templated
|
||||
.mmu_bp (etx_rr), // Templated
|
||||
.mi_en (mi_mmu_en), // Templated
|
||||
.mi_we (mi_we),
|
||||
.mi_addr (mi_addr[14:0]),
|
||||
.mi_din (mi_din[DW-1:0]),
|
||||
.emesh_access_in (etx_remap_access), // Templated
|
||||
.emesh_packet_in (etx_remap_packet[PW-1:0]), // Templated
|
||||
.emesh_rd_wait (etx_rd_wait), // Templated
|
||||
.emesh_wr_wait (etx_wr_wait)); // Templated
|
||||
|
||||
|
||||
/************************************************************/
|
||||
/*ELINK PROTOCOL LOGIC */
|
||||
/************************************************************/
|
||||
/*etx_protocol AUTO_TEMPLATE (
|
||||
.etx_rd_wait (etx_rd_wait),
|
||||
.etx_wr_wait (etx_wr_wait),
|
||||
.etx_\(.*\) (emmu_\1[]),
|
||||
.etx_wait (etx_wait),
|
||||
);
|
||||
*/
|
||||
|
||||
defparam etx_protocol.ID=ID;
|
||||
etx_protocol etx_protocol (
|
||||
/*AUTOINST*/
|
||||
// Outputs
|
||||
.etx_rd_wait (etx_rd_wait), // Templated
|
||||
.etx_wr_wait (etx_wr_wait), // Templated
|
||||
.tx_frame_par (tx_frame_par[7:0]),
|
||||
.tx_data_par (tx_data_par[63:0]),
|
||||
// Inputs
|
||||
.reset (reset),
|
||||
.clk (clk),
|
||||
.etx_access (emmu_access), // Templated
|
||||
.etx_packet (emmu_packet[PW-1:0]), // Templated
|
||||
.tx_enable (tx_enable),
|
||||
.gpio_data (gpio_data[8:0]),
|
||||
.gpio_enable (gpio_enable),
|
||||
.tx_rd_wait (tx_rd_wait),
|
||||
.tx_wr_wait (tx_wr_wait));
|
||||
|
||||
endmodule // elink
|
||||
// Local Variables:
|
||||
// verilog-library-directories:("." "../../emmu/hdl" "../../memory/hdl" "../../edma/hdl/")
|
||||
// End:
|
||||
|
||||
|
||||
/*
|
||||
Copyright (C) 2015 Adapteva, Inc.
|
||||
|
||||
Contributed by Andreas Olofsson <andreas@adapteva.com>
|
||||
|
||||
This program is free software: you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation, either version 3 of the License, or
|
||||
(at your option) any later version.This program is distributed in the hope
|
||||
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
|
||||
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details. You should have received a copy
|
||||
of the GNU General Public License along with this program (see the file
|
||||
COPYING). If not, see <http://www.gnu.org/licenses/>.
|
||||
*/
|
||||
Loading…
x
Reference in New Issue
Block a user