Fixing syntax errors found by surelog

stdlib/hdl/oh_and2.v

@@ -9,12 +9,12 @@ module oh_and2  #(parameter N  = 1,        // block width
 		  parameter SYN  = "TRUE",    // synthesizable
 		  parameter TYPE = "DEFAULT"  // implementation type
 		  )
-   #(parameter N = 1 ) // array width
    (
     input [N-1:0]  a,
     input [N-1:0]  b,
     output [N-1:0] z
     );
+
    generate
       if(SYN == "TRUE")  begin
 	 assign z = a & b;

stdlib/hdl/oh_reg0.v

@@ -5,10 +5,9 @@
 //# License:  MIT (see LICENSE file in OH! repository)                        #
 //#############################################################################
 
-module ohr_reg0 #(parameter N = 1            // data width
-		  )
-   ( input           nreset, //async active low reset
-     input 	     clk, // clk, latch when clk=0
+module ohr_reg0 #(parameter N = 1)       // data width
+   ( input          nreset, //async active low reset
+     input 	    clk, // clk, latch when clk=0
      input [N-1:0]  in, // input data
      output [N-1:0] out  // output data (stable/latched when clk=1)
      );