From eb16df1e3c5df715d7c234bd0dd82d75c6968d4c Mon Sep 17 00:00:00 2001
From: aolofsson <andreas@zeroasic.com>
Date: Thu, 23 Sep 2021 09:58:08 -0400
Subject: [PATCH] Fixing syntax errors found by surelog

---
 {stdlib => mathlib}/hdl/oh_counter.v    | 0
 stdlib/hdl/oh_and2.v                    | 2 +-
 {mathlib => stdlib}/hdl/oh_bin2gray.v   | 0
 {mathlib => stdlib}/hdl/oh_bin2onehot.v | 0
 stdlib/hdl/oh_reg0.v                    | 7 +++----
 5 files changed, 4 insertions(+), 5 deletions(-)
 rename {stdlib => mathlib}/hdl/oh_counter.v (100%)
 rename {mathlib => stdlib}/hdl/oh_bin2gray.v (100%)
 rename {mathlib => stdlib}/hdl/oh_bin2onehot.v (100%)

diff --git a/stdlib/hdl/oh_counter.v b/mathlib/hdl/oh_counter.v
similarity index 100%
rename from stdlib/hdl/oh_counter.v
rename to mathlib/hdl/oh_counter.v
diff --git a/stdlib/hdl/oh_and2.v b/stdlib/hdl/oh_and2.v
index a3e7cb2..14c6504 100644
--- a/stdlib/hdl/oh_and2.v
+++ b/stdlib/hdl/oh_and2.v
@@ -9,12 +9,12 @@ module oh_and2  #(parameter N  = 1,        // block width
 		  parameter SYN  = "TRUE",    // synthesizable
 		  parameter TYPE = "DEFAULT"  // implementation type
 		  )
-   #(parameter N = 1 ) // array width
    (
     input [N-1:0]  a,
     input [N-1:0]  b,
     output [N-1:0] z
     );
+
    generate
       if(SYN == "TRUE")  begin
 	 assign z = a & b;
diff --git a/mathlib/hdl/oh_bin2gray.v b/stdlib/hdl/oh_bin2gray.v
similarity index 100%
rename from mathlib/hdl/oh_bin2gray.v
rename to stdlib/hdl/oh_bin2gray.v
diff --git a/mathlib/hdl/oh_bin2onehot.v b/stdlib/hdl/oh_bin2onehot.v
similarity index 100%
rename from mathlib/hdl/oh_bin2onehot.v
rename to stdlib/hdl/oh_bin2onehot.v
diff --git a/stdlib/hdl/oh_reg0.v b/stdlib/hdl/oh_reg0.v
index 2841fd1..87a2b09 100644
--- a/stdlib/hdl/oh_reg0.v
+++ b/stdlib/hdl/oh_reg0.v
@@ -5,10 +5,9 @@
 //# License:  MIT (see LICENSE file in OH! repository)                        #
 //#############################################################################
 
-module ohr_reg0 #(parameter N = 1            // data width
-		  )
-   ( input           nreset, //async active low reset
-     input 	     clk, // clk, latch when clk=0
+module ohr_reg0 #(parameter N = 1)       // data width
+   ( input          nreset, //async active low reset
+     input 	    clk, // clk, latch when clk=0
      input [N-1:0]  in, // input data
      output [N-1:0] out  // output data (stable/latched when clk=1)
      );