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Fixing basic FIFO bug

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- count was not fully reset...
- adding parameter values to memory instance
This commit is contained in:
Andreas Olofsson 2015-12-10 19:32:15 -05:00
parent 22976b781d
commit ec627556f7
1 changed files with 13 additions and 9 deletions
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22
common/hdl/oh_fifo_sync.v
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@ -1,6 +1,6 @@
module oh_fifo_sync (/*AUTOARG*/ module oh_fifo_sync (/*AUTOARG*/
// Outputs // Outputs
dout, empty, full, almost_full, dout, empty, full, almost_full, count,
// Inputs // Inputs
clk, nreset, din, wr_en, rd_en clk, nreset, din, wr_en, rd_en
); );
@ -34,6 +34,7 @@ module oh_fifo_sync (/*AUTOARG*/
output empty; output empty;
output full; output full;
output almost_full; output almost_full;
output [AW:0] count;
//##################################################################### //#####################################################################
//# BODY //# BODY
@ -52,28 +53,31 @@ module oh_fifo_sync (/*AUTOARG*/
begin begin
wr_addr[AW-1:0] <= 'd0; wr_addr[AW-1:0] <= 'd0;
rd_addr[AW-1:0] <= 'b0; rd_addr[AW-1:0] <= 'b0;
count[AW-1:0] <= 'b0; count[AW:0] <= 'b0;
end end
else if(wr_en & rd_en) else if(wr_en & rd_en)
begin begin
wr_addr <= wr_addr + 'd1; wr_addr[AW-1:0] <= wr_addr[AW-1:0] + 'd1;
rd_addr <= rd_addr + 'd1; rd_addr[AW-1:0] <= rd_addr[AW-1:0] + 'd1;
end end
else if(wr_en) else if(wr_en)
begin begin
wr_addr <= wr_addr + 'd1; wr_addr[AW-1:0] <= wr_addr[AW-1:0] + 'd1;
count <= count + 'd1; count[AW:0] <= count[AW:0] + 'd1;
end end
else if(rd_en) else if(rd_en)
begin begin
rd_addr <= rd_addr + 'd1; rd_addr[AW-1:0] <= rd_addr[AW-1:0] + 'd1;
count <= count - 'd1; count[AW:0] <= count[AW:0] - 'd1;
end end
// GENERIC DUAL PORTED MEMORY // GENERIC DUAL PORTED MEMORY
defparam mem.DW=DW; defparam mem.DW=DW;
defparam mem.AW=AW; defparam mem.AW=AW;
oh_memory_dp mem ( oh_memory_dp
#(.DW(DW),
.AW(AW))
mem (
// Outputs // Outputs
.rd_data (dout[DW-1:0]), .rd_data (dout[DW-1:0]),
// Inputs // Inputs