Packet interface changes

elink/dv/dv_elink_tb.v

@@ -1,6 +1,7 @@
 module dv_elink_tb();
    parameter AW=32;
    parameter DW=32;
+   parameter PW=104;
    parameter CW=2;    //number of clocks to send int
    parameter MW=104;
    parameter MAW=10;    
@@ -16,14 +17,16 @@ module dv_elink_tb();
    reg 		 go;
    reg [1:0] 	 datamode;
    reg 		 ext_access;
-   reg           ext_write;
+   reg 		 ext_write;
-   reg [1:0]     ext_datamode;
+   reg [1:0] 	 ext_datamode;
    reg [3:0]     ext_ctrlmode;            
    reg [31:0]    ext_dstaddr;
    reg [31:0]    ext_data;
    reg [31:0]    ext_srcaddr;   
    reg           ext_wr_wait;
    reg           ext_rd_wait;
+   wire [PW-1:0] ext_packet;
+
    reg 		 init;
    reg [MW-1:0]  stimarray[MD-1:0];
    reg [MW-1:0]  transaction;
@@ -58,7 +61,6 @@ module dv_elink_tb();
 	  reset    = 1'b1;    // reset is active
           go       = 1'b0;
 	  clk[1:0] = 2'b0;
-	  datamode = 2'b10;	
 	#400 
 
 `ifdef AUTO
@@ -131,18 +133,27 @@ always @ (posedge clkstim)
    /*AUTOWIRE*/
    // Beginning of automatic wires (for undeclared instantiated-module outputs)
    wire			dut_access;		// From dv_elink of dv_elink.v
-   wire [3:0]		dut_ctrlmode;		// From dv_elink of dv_elink.v
-   wire [31:0]		dut_data;		// From dv_elink of dv_elink.v
-   wire [1:0]		dut_datamode;		// From dv_elink of dv_elink.v
-   wire [31:0]		dut_dstaddr;		// From dv_elink of dv_elink.v
    wire			dut_failed;		// From dv_elink of dv_elink.v
+   wire [PW-1:0]	dut_packet;		// From dv_elink of dv_elink.v
    wire			dut_passed;		// From dv_elink of dv_elink.v
    wire			dut_rd_wait;		// From dv_elink of dv_elink.v
-   wire [31:0]		dut_srcaddr;		// From dv_elink of dv_elink.v
    wire			dut_wr_wait;		// From dv_elink of dv_elink.v
-   wire			dut_write;		// From dv_elink of dv_elink.v
+   wire [PW-1:0]	packet_out;		// From e2p of emesh2packet.v
    // End of automatics
    
+   emesh2packet e2p (/*AUTOINST*/
+		     // Outputs
+		     .packet_out	(ext_packet[PW-1:0]),
+		     // Inputs
+		     .access_in		(ext_access),
+		     .write_in		(ext_write),
+		     .datamode_in	(ext_datamode[1:0]),
+		     .ctrlmode_in	(ext_ctrlmode[3:0]),
+		     .dstaddr_in	(ext_dstaddr[AW-1:0]),
+		     .data_in		(ext_data[DW-1:0]),
+		     .srcaddr_in	(ext_srcaddr[AW-1:0]));
+   
+   
    //dut
    dv_elink dv_elink(/*AUTOINST*/
 		     // Outputs
@@ -151,26 +162,19 @@ always @ (posedge clkstim)
 		     .dut_rd_wait	(dut_rd_wait),
 		     .dut_wr_wait	(dut_wr_wait),
 		     .dut_access	(dut_access),
-		     .dut_write		(dut_write),
+		     .dut_packet	(dut_packet[PW-1:0]),
-		     .dut_datamode	(dut_datamode[1:0]),
-		     .dut_ctrlmode	(dut_ctrlmode[3:0]),
-		     .dut_dstaddr	(dut_dstaddr[31:0]),
-		     .dut_srcaddr	(dut_srcaddr[31:0]),
-		     .dut_data		(dut_data[31:0]),
 		     // Inputs
 		     .clk		(clk[CW-1:0]),
 		     .reset		(reset),
 		     .ext_access	(ext_access),
-		     .ext_write		(ext_write),
+		     .ext_packet	(ext_packet[PW-1:0]),
-		     .ext_datamode	(ext_datamode[1:0]),
-		     .ext_ctrlmode	(ext_ctrlmode[3:0]),
-		     .ext_dstaddr	(ext_dstaddr[31:0]),
-		     .ext_data		(ext_data[31:0]),
-		     .ext_srcaddr	(ext_srcaddr[31:0]),
 		     .ext_rd_wait	(ext_rd_wait),
 		     .ext_wr_wait	(ext_wr_wait));
   
 endmodule // dv_elink_tb
+// Local Variables:
+// verilog-library-directories:("." "../../common/hdl")
+// End:
 
 
 /*

elink/dv/elink.cmd

@@ -6,8 +6,9 @@ dv_elink_tb.v
 -y ../../xilibs/hdl
 -y ../../common/hdl
 -y ../../memory/hdl
--y ../../embox/hdl
+-y ../../emailbox/hdl
 -y ../../emmu/hdl
+-y ../../edma/hdl
 
 
 

elink/dv/emesh_monitor.v

@@ -1,14 +1,14 @@
 /* verilator lint_off WIDTH */
 module emesh_monitor(/*AUTOARG*/
    // Inputs
-   clk, reset, itrace, etime, emesh_access, emesh_write,
+   clk, reset, itrace, etime, emesh_access, emesh_packet, emesh_wait
-   emesh_datamode, emesh_ctrlmode, emesh_dstaddr, emesh_data,
-   emesh_srcaddr, emesh_wait
    );
    parameter AW     =  32;
    parameter DW     =  32;
    parameter NAME   =  "cpu";
-
+   parameter PW     = 104;
+   
+   
    //BASIC INTERFACE
    input            clk;
    input            reset;
@@ -17,12 +17,7 @@ module emesh_monitor(/*AUTOARG*/
    
    //MESH TRANSCTION
    input            emesh_access;
-   input            emesh_write;
+   input [PW-1:0]   emesh_packet;   
-   input [1:0]      emesh_datamode;
-   input [3:0] 	    emesh_ctrlmode;
-   input [AW-1:0]   emesh_dstaddr;
-   input [DW-1:0]   emesh_data;
-   input [AW-1:0]   emesh_srcaddr;
    input            emesh_wait;
 
    //core name for trace
@@ -38,7 +33,8 @@ module emesh_monitor(/*AUTOARG*/
      if(itrace & ~reset & emesh_access & ~emesh_wait)
        begin	     	 
 	  //$fwrite(ftrace, "TIME=%h\n",etime[31:0]);
-	  $fwrite(ftrace, "%h_%h_%h_%h\n",emesh_srcaddr[AW-1:0], emesh_data[DW-1:0],emesh_dstaddr[DW-1:0],{emesh_ctrlmode[3:0],emesh_datamode[1:0],emesh_write,emesh_access});
+	  $fwrite(ftrace, "%h_%h_%h_%h\n",emesh_packet[103:72], emesh_packet[71:40],emesh_packet[39:8],
+		                          {emesh_packet[7:4],emesh_packet[3:2],emesh_packet[1],emesh_access});
        end   
 endmodule // emesh_monitor