Moving simctrl to testbench

- Cleaning up interfaces
- Adding more universal parameters to testbench top

stdlib/testbench/tb_oh_random.v

@@ -1,43 +1,58 @@
-module testbench();
+//#############################################################################
+//# Function: DUT wrapper
+//#############################################################################
+//# Author:   Andreas Olofsson                                                #
+//# License:  MIT (see LICENSE file in OH! repository)                        #
+//#############################################################################
 
-   localparam N = 32;
+module tb_dut
+  #(parameter PW              = 256,      // packet width
+    parameter N               = 32,       // ctrl/status width
+    parameter SEED            = 0,        // random seed
+    parameter TARGET          = "DEFAULT" // physical synthesis/sim target
+    )
+   (// basic test interface
+    input 	    clk, // standard clock used for interface
+    input 	    fastclk, // fast clock (optional for core)
+    input 	    slowclk, // fast clock (optional for core)
+    input 	    nreset, // async active low reset
+    input 	    go, // go dut (if not self-booting)
+    input [N-1:0]   ctrl, // env generic ctrl vector
+    // environment packet interface
+    input 	    valid, // env packet valid signal
+    input [PW-1:0]  packet, // env packet to drive
+    input 	    ready, // env is ready for packet
+    // dut status signals
+    output 	    dut_active, // dut reset sequence done
+    output 	    dut_error, // per cycle error signal
+    output 	    dut_done, // dut is done
+    output [N-1:0]  dut_status, // dut generic status vector
+    // dut response packets
+    output 	    dut_valid, //dut packet valid signal
+    output [PW-1:0] dut_packet, // dut packet to drive
+    output 	    dut_ready // dut is ready for packet
+    );
+
+   // wrapper signals (not used for this one)
+   assign dut_active = 1'b1;
+   assign dut_ready  = 1'b1;
+   assign dut_error  = 1'b0;
+   assign dut_done   = 1'b0;
+   assign dut_valid  = 1'b0;
 
    /*AUTOINPUT*/
    /*AUTOWIRE*/
-   // Beginning of automatic wires (for undeclared instantiated-module outputs)
-   wire			clk1;			// From oh_simctrl of oh_simctrl.v
-   wire			clk2;			// From oh_simctrl of oh_simctrl.v
-   wire			nreset;			// From oh_simctrl of oh_simctrl.v
-   wire [N-1:0]		out;			// From oh_random of oh_random.v
-   wire			start;			// From oh_simctrl of oh_simctrl.v
-   wire			vdd;			// From oh_simctrl of oh_simctrl.v
-   wire			vss;			// From oh_simctrl of oh_simctrl.v
-   // End of automatics
-
-   oh_random #(.N(N))
-   oh_random(.en		(1'b1),
-	     .clk		(clk1),
+   oh_random #(.N(N),
+	       .SEED(SEED))
+   oh_random(.en	(go),
+	     .mask	({(N){1'b1}}),
+	     .out	(dut_status[N-1:0]),
 	     /*AUTOINST*/
-	     // Outputs
-	     .out			(out[N-1:0]),
 	     // Inputs
+	     .clk			(clk),
 	     .nreset			(nreset));
 
-   oh_simctrl oh_simctrl(//TODO: implement
-			.stim_done	(1'b0),
-			.test_done	(1'b0),
-			.test_diff	(1'b0),
-			.dut_active     (1'b1),
-			/*AUTOINST*/
-			 // Outputs
-			 .nreset		(nreset),
-			 .clk1			(clk1),
-			 .clk2			(clk2),
-			 .start			(start),
-			 .vdd			(vdd),
-			 .vss			(vss));
-
 endmodule // tb
 // Local Variables:
-// verilog-library-directories:("." "../hdl")
+// verilog-library-directories:("." "../rtl")
 // End:

stdlib/testbench/testbench.v

@@ -1,24 +1,24 @@
 //#############################################################################
-//# Function: Common testbench to run in Simulator of FPGA                    #
+//# Function: Common testbench for simulator and fpga                         #
 //#############################################################################
 //# Author:   Andreas Olofsson                                                #
 //# License:  MIT (see LICENSE file in OH! repository)                        #
 //#############################################################################
 
 module testbench
-  #(parameter PW              = 256,      // packet width
-    parameter CW              = 16,       // control width
-    parameter N               = 36,       // ctrl/status width
-    parameter PERIOD_CLK      = 10,       // core clock period
-    parameter PERIOD_FASTCLK  = 20,       // fast clock period
-    parameter PERIOD_SLOWCLK  = 20,       // slow clock period
-    parameter TIMEOUT         = 5000,     // timeout value
-    parameter RANDOMIZE       = 0,        // 1=randomize period
-    parameter SIMULATE        = 1,        // 1=VERILOG SIM
-    parameter FILENAME        = "NONE",   // Simulus hexfile for $readmemh
-    parameter DEPTH           = 8192,     // Simulus memory depth
-
-    parameter TARGET          = "DEFAULT" // physical synthesis/sim target
+  #(parameter PW             = 256,         // packet width
+    parameter CW             = 16,         // control width
+    parameter N              = 32,          // ctrl/status width
+    parameter PERIOD_CLK     = 10,          // core clock period
+    parameter PERIOD_FASTCLK = 20,          // fast clock period
+    parameter PERIOD_SLOWCLK = 20,          // slow clock period
+    parameter TIMEOUT        = 5000,        // timeout value
+    parameter RANDOMIZE      = 0,           // 1=randomize period
+    parameter SIMULATE       = 1,           // 1=VERILOG SIM
+    parameter FILENAME       = "NONE",      // Simulus hexfile for $readmemh
+    parameter DEPTH          = 8192,        // simulus memory depth
+    parameter SEED           = 32'haaaaaaaa,// seed for random generation
+    parameter TARGET         = "DEFAULT"    // physical synthesis/sim target
     )
    (
     // control signals to drive
@@ -111,6 +111,7 @@ module testbench
 	  */
    tb_dut #(.PW(PW),
 	    .N(N),
+	    .SEED(SEED),
 	    .TARGET(TARGET))
    tb_dut(.valid		(tb_valid),
 	  .packet		(tb_packet[PW-1:0]),