From edaa41dac7e890ba8025ca890362fb8b65dea324 Mon Sep 17 00:00:00 2001 From: aolofsson Date: Mon, 26 Jul 2021 11:32:43 -0400 Subject: [PATCH] Adding asic_add block to abs circuit --- common/hdl/oh_abs.v | 36 +++++++++++++++++++++++++----------- 1 file changed, 25 insertions(+), 11 deletions(-) diff --git a/common/hdl/oh_abs.v b/common/hdl/oh_abs.v index f13a4b0..3da264d 100644 --- a/common/hdl/oh_abs.v +++ b/common/hdl/oh_abs.v @@ -2,20 +2,34 @@ //# Function: Calculates absolute value of input # //############################################################################# //# Author: Andreas Olofsson # -//# License: MIT (see LICENSE file in OH! repository) # +//# License: MIT (see LICENSE file in OH! repository) # //############################################################################# -module oh_abs #(parameter DW = 2) // data width +module oh_abs + #(parameter N = 32, // block width + parameter SYN = "TRUE", // synthesizable + parameter TYPE = "DEFAULT" // implementation type + ) ( - input [DW-1:0] in, //input operand - output [DW-1:0] out, //out = abs(in) (signed two's complement) - output overflow //high for max negative # + input [N-1:0] in, // input operand + output [N-1:0] out, // out = abs(in) (signed two's complement) + output overflow // high for max negative # ); - - assign out[DW-1:0] = in[DW-1] ? ~in[DW-1:0] + 1'b1 : - in[DW-1:0]; - assign overflow = in[DW-1] & ~(|in[DW-2:0]); - -endmodule // oh_abs + generate + if(SYN == "TRUE") begin + assign out[N-1:0] = in[N-1] ? ~in[N-1:0] + 1'b1 : in[N-1:0]; + assign overflow = in[N-1] & ~(|in[N-2:0]); + end + else begin + asic_abs #(.TYPE(TYPE), + .N(N)) + asic_abs(// Outputs + .out (out[N-1:0]), + .overflow (overflow), + // Inputs + .in (in[N-1:0])); + end + endgenerate +endmodule