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Fixed ODDR model for SAME_EDGE mode

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This commit is contained in:
Andreas Olofsson 2015-05-15 09:46:08 -04:00
parent 836c4a65a8
commit ee363f6119
1 changed files with 16 additions and 10 deletions
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26
xilibs/hdl/ODDR.v
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@ -1,3 +1,5 @@
/*WARNING: ONLY SAME EDGE SUPPORTED FOR NOW*/
//D1,D2 sampled on rising edge of C
module ODDR (/*AUTOARG*/
// Outputs
Q,
@ -9,16 +11,17 @@ module ODDR (/*AUTOARG*/
parameter INIT=0; //Q init value
parameter SRTYPE=0;//"SYNC", "ASYNC"
input C; // Clock input
input CE; // Clock enable input
input D1; // Data input1
input D2; // Data input2
input R; // Reset (depends on SRTYPE)
input S; // Active high asynchronous pin
output Q; // Data Output that connects to the IOB pad
input C; // Clock input
input CE; // Clock enable input
input D1; // Data input1
input D2; // Data input2
input R; // Reset (depends on SRTYPE)
input S; // Active high asynchronous pin
output Q; // Data Output that connects to the IOB pad
reg Q1,Q2;
reg Q2_reg;
//Generate different logic based on parameters
//Only doing same edge and async reset for now
@ -34,8 +37,11 @@ module ODDR (/*AUTOARG*/
Q2 <= 1'b0;
else
Q2 <= D2;
assign Q = C ? Q1 : Q2;
always @ (negedge C)
Q2_reg <= Q2;
assign Q = C ? Q1 : Q2_reg;
endmodule // ODDR