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Clock cleanup
-Adding enable signal to clock out. Definitely right decision to keep separate bit from the divider field. -Fixed settings for to fit new register field -XILINX version is still broken!!
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@ -22,7 +22,7 @@ module eclocks (/*AUTOARG*/
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// Outputs
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cclk_p, cclk_n, tx_lclk, tx_lclk_out, tx_lclk_par,
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// Inputs
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clkin, hard_reset, ecfg_clk_settings, bypass_clocks
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clkin, hard_reset, ecfg_clk_settings, clkbypass
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);
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// Parameters must be set as follows:
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@ -43,7 +43,7 @@ module eclocks (/*AUTOARG*/
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input clkin; // primary input clock
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input hard_reset; //
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input [15:0] ecfg_clk_settings; // clock settings
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input [2:0] bypass_clocks; // for bypassing PLL
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input [2:0] clkbypass; // for bypassing PLL
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//Output Clocks
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@ -53,8 +53,14 @@ module eclocks (/*AUTOARG*/
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output tx_lclk_par; // lclk/8 slow clock for tx parallel logic
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// Wires
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wire cclk_en;
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wire lclk_en;
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//Register decoding
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assign cclk_en=ecfg_clk_settings[0];
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assign lclk_en=ecfg_clk_settings[1];
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`ifdef TARGET_XILINX
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wire clkfb;
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wire pll_cclk; //full speed cclk
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@ -117,7 +123,9 @@ generate
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.CLKFBIN(clkfb) //feedback clock input
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);
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//TODO!! Redesign this all together!!!
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// Output buffering
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BUFG cclk_buf (.O (cclk_base), .I (pll_cclk));
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BUFG cclk_div_buf (.O (cclk_div), .I (pll_cclk_div));
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@ -131,18 +139,18 @@ generate
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// Create adjustable (but fast) CCLK
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wire rxi_cclk_out;
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reg [8:1] cclk_pattern;
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reg [3:0] clk_div_sync;
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reg [4:0] clk_div_sync;
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reg enb_sync;
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always @ (posedge cclk_div) begin // Might need x-clock TIG here
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clk_div_sync <= ecfg_clk_settings[3:0];
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enb_sync <= ~(|ecfg_clk_settings[3:0]);
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clk_div_sync <= {cclk_en,ecfg_clk_settings[7:4]};
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if(enb_sync)
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case(clk_div_sync)
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4'h0: cclk_pattern <= 8'd0; // Clock OFF
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4'h7: cclk_pattern <= 8'b10101010; // Divide by 1
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4'h0: cclk_pattern <= 8'b10101010; // Divide by 1
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4'h6: cclk_pattern <= 8'b11001100; // Divide by 2
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4'h5: cclk_pattern <= 8'b11110000; // Divide by 4
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default: cclk_pattern <= {8{~cclk_pattern[1]}}; // /8
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@ -218,7 +226,11 @@ endgenerate
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`elsif TARGET_CLEAN
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wire cclk;
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wire lclk_par;
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wire lclk;
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wire lclk_out;
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clock_divider cclk_divider(
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// Outputs
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.clkout (cclk),
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@ -226,33 +238,38 @@ endgenerate
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// Inputs
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.clkin (clkin),
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.reset (hard_reset),
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.divcfg (ecfg_clk_settings[3:0])
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.divcfg (ecfg_clk_settings[7:4])
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);
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assign cclk_p = cclk;
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assign cclk_n = ~cclk;
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assign cclk_p = cclk & cclk_en ;
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assign cclk_n = ~cclk_p;
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clock_divider lclk_divider(
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// Outputs
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.clkout (tx_lclk),
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.clkout90 (tx_lclk_out),
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.clkout (lclk),
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.clkout90 (lclk_out),
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// Inputs
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.clkin (clkin),
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.reset (hard_reset),
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.divcfg (ecfg_clk_settings[7:4])
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.divcfg (ecfg_clk_settings[11:8])
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);
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clock_divider lclk_par_divider(
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// Outputs
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.clkout (tx_lclk_par),
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.clkout (lclk_par),
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.clkout90 (),
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// Inputs
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.clkin (clkin),
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.reset (hard_reset),
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.divcfg (ecfg_clk_settings[7:4] + 4'd2)
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.divcfg (ecfg_clk_settings[11:8] + 4'd2)
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);
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//Clock enables
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assign tx_lclk_par = lclk_par & lclk_en;
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assign tx_lclk = lclk & lclk_en;
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assign tx_lclk_out = lclk_out & lclk_en;
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`endif
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