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Clock cleanup

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-Adding enable signal to clock out. Definitely right decision to keep
separate bit from the divider field.
-Fixed settings for to fit new register field
-XILINX version is still broken!!
This commit is contained in:
Andreas Olofsson 2015-04-18 16:24:26 -04:00
parent b30dbe6005
commit f141a0e320
1 changed files with 35 additions and 18 deletions
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45
elink/hdl/eclocks.v
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@ -22,7 +22,7 @@ module eclocks (/*AUTOARG*/
// Outputs // Outputs
cclk_p, cclk_n, tx_lclk, tx_lclk_out, tx_lclk_par, cclk_p, cclk_n, tx_lclk, tx_lclk_out, tx_lclk_par,
// Inputs // Inputs
clkin, hard_reset, ecfg_clk_settings, bypass_clocks clkin, hard_reset, ecfg_clk_settings, clkbypass
); );
// Parameters must be set as follows: // Parameters must be set as follows:
@ -43,7 +43,7 @@ module eclocks (/*AUTOARG*/
input clkin; // primary input clock input clkin; // primary input clock
input hard_reset; // input hard_reset; //
input [15:0] ecfg_clk_settings; // clock settings input [15:0] ecfg_clk_settings; // clock settings
input [2:0] bypass_clocks; // for bypassing PLL input [2:0] clkbypass; // for bypassing PLL
//Output Clocks //Output Clocks
@ -53,8 +53,14 @@ module eclocks (/*AUTOARG*/
output tx_lclk_par; // lclk/8 slow clock for tx parallel logic output tx_lclk_par; // lclk/8 slow clock for tx parallel logic
// Wires // Wires
wire cclk_en;
wire lclk_en;
//Register decoding
assign cclk_en=ecfg_clk_settings[0];
assign lclk_en=ecfg_clk_settings[1];
`ifdef TARGET_XILINX `ifdef TARGET_XILINX
wire clkfb; wire clkfb;
wire pll_cclk; //full speed cclk wire pll_cclk; //full speed cclk
@ -118,6 +124,8 @@ generate
); );
//TODO!! Redesign this all together!!!
// Output buffering // Output buffering
BUFG cclk_buf (.O (cclk_base), .I (pll_cclk)); BUFG cclk_buf (.O (cclk_base), .I (pll_cclk));
BUFG cclk_div_buf (.O (cclk_div), .I (pll_cclk_div)); BUFG cclk_div_buf (.O (cclk_div), .I (pll_cclk_div));
@ -131,18 +139,18 @@ generate
// Create adjustable (but fast) CCLK // Create adjustable (but fast) CCLK
wire rxi_cclk_out; wire rxi_cclk_out;
reg [8:1] cclk_pattern; reg [8:1] cclk_pattern;
reg [3:0] clk_div_sync; reg [4:0] clk_div_sync;
reg enb_sync; reg enb_sync;
always @ (posedge cclk_div) begin // Might need x-clock TIG here always @ (posedge cclk_div) begin // Might need x-clock TIG here
clk_div_sync <= ecfg_clk_settings[3:0]; clk_div_sync <= {cclk_en,ecfg_clk_settings[7:4]};
enb_sync <= ~(|ecfg_clk_settings[3:0]);
if(enb_sync) if(enb_sync)
case(clk_div_sync) case(clk_div_sync)
4'h0: cclk_pattern <= 8'd0; // Clock OFF 4'h0: cclk_pattern <= 8'd0; // Clock OFF
4'h7: cclk_pattern <= 8'b10101010; // Divide by 1 4'h0: cclk_pattern <= 8'b10101010; // Divide by 1
4'h6: cclk_pattern <= 8'b11001100; // Divide by 2 4'h6: cclk_pattern <= 8'b11001100; // Divide by 2
4'h5: cclk_pattern <= 8'b11110000; // Divide by 4 4'h5: cclk_pattern <= 8'b11110000; // Divide by 4
default: cclk_pattern <= {8{~cclk_pattern[1]}}; // /8 default: cclk_pattern <= {8{~cclk_pattern[1]}}; // /8
@ -218,6 +226,10 @@ endgenerate
`elsif TARGET_CLEAN `elsif TARGET_CLEAN
wire cclk; wire cclk;
wire lclk_par;
wire lclk;
wire lclk_out;
clock_divider cclk_divider( clock_divider cclk_divider(
// Outputs // Outputs
@ -226,34 +238,39 @@ endgenerate
// Inputs // Inputs
.clkin (clkin), .clkin (clkin),
.reset (hard_reset), .reset (hard_reset),
.divcfg (ecfg_clk_settings[3:0]) .divcfg (ecfg_clk_settings[7:4])
); );
assign cclk_p = cclk; assign cclk_p = cclk & cclk_en ;
assign cclk_n = ~cclk; assign cclk_n = ~cclk_p;
clock_divider lclk_divider( clock_divider lclk_divider(
// Outputs // Outputs
.clkout (tx_lclk), .clkout (lclk),
.clkout90 (tx_lclk_out), .clkout90 (lclk_out),
// Inputs // Inputs
.clkin (clkin), .clkin (clkin),
.reset (hard_reset), .reset (hard_reset),
.divcfg (ecfg_clk_settings[7:4]) .divcfg (ecfg_clk_settings[11:8])
); );
clock_divider lclk_par_divider( clock_divider lclk_par_divider(
// Outputs // Outputs
.clkout (tx_lclk_par), .clkout (lclk_par),
.clkout90 (), .clkout90 (),
// Inputs // Inputs
.clkin (clkin), .clkin (clkin),
.reset (hard_reset), .reset (hard_reset),
.divcfg (ecfg_clk_settings[7:4] + 4'd2) .divcfg (ecfg_clk_settings[11:8] + 4'd2)
); );
//Clock enables
assign tx_lclk_par = lclk_par & lclk_en;
assign tx_lclk = lclk & lclk_en;
assign tx_lclk_out = lclk_out & lclk_en;
`endif `endif