FPGA/oh
1
0
Fork 0
mirror of https://github.com/aolofsson/oh.git synced 2025-01-17 20:02:53 +08:00
Code Issues Projects Releases Wiki Activity

Adding high level single ported memory

Browse Source
This commit is contained in:
Andreas Olofsson 2015-04-18 16:11:21 -04:00
parent 9c24869d72
commit f606fc5794
2 changed files with 69 additions and 53 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

64
memory/hdl/fifo_sync.v
View File

@ -25,15 +25,15 @@ module fifo_sync
output reg wr_full
);
reg [AW-1:0] waddr;
reg [AW-1:0] raddr;
reg [AW-1:0] wr_addr;
reg [AW-1:0] rd_addr;
reg [AW-1:0] count;
always @ ( posedge clk ) begin
if( reset )
begin
waddr[AW-1:0] <= 'd0;
raddr[AW-1:0] <= 'b0;
wr_addr[AW-1:0] <= 'd0;
rd_addr[AW-1:0] <= 'b0;
count[AW-1:0] <= 'b0;
rd_empty <= 1'b1;
wr_full <= 1'b0;
@ -41,12 +41,12 @@ module fifo_sync
begin
if( wr_en & rd_en )
begin
waddr <= waddr + 'd1;
raddr <= raddr + 'd1;
wr_addr <= wr_addr + 'd1;
rd_addr <= rd_addr + 'd1;
end
else if( wr_en )
begin
waddr <= waddr + 'd1;
wr_addr <= wr_addr + 'd1;
count <= count + 'd1;
rd_empty <= 1'b0;
if( & count )
@ -54,7 +54,7 @@ module fifo_sync
end
else if( rd_en )
begin
raddr <= raddr + 'd1;
rd_addr <= rd_addr + 'd1;
count <= count - 'd1;
wr_full <= 1'b0;
if( count == 'd1 )
@ -71,28 +71,52 @@ module fifo_sync
(
.DPO(rd_data[dn] ), // Read-only 1-bit data output
.SPO(), // Rw/ 1-bit data output
.A0(waddr[0]), // Rw/ address[0] input bit
.A1(waddr[1]), // Rw/ address[1] input bit
.A2(waddr[2]), // Rw/ address[2] input bit
.A3(waddr[3]), // Rw/ address[3] input bit
.A4(waddr[4]), // Rw/ address[4] input bit
.A0(wr_addr[0]), // Rw/ address[0] input bit
.A1(wr_addr[1]), // Rw/ address[1] input bit
.A2(wr_addr[2]), // Rw/ address[2] input bit
.A3(wr_addr[3]), // Rw/ address[3] input bit
.A4(wr_addr[4]), // Rw/ address[4] input bit
.D(wr_data[dn]), // Write 1-bit data input
.DPRA0(raddr[0]), // Read-only address[0] input bit
.DPRA1(raddr[1]), // Read-only address[1] input bit
.DPRA2(raddr[2]), // Read-only address[2] input bit
.DPRA3(raddr[3]), // Read-only address[3] input bit
.DPRA4(raddr[4]), // Read-only address[4] input bit
.DPRA0(rd_addr[0]), // Read-only address[0] input bit
.DPRA1(rd_addr[1]), // Read-only address[1] input bit
.DPRA2(rd_addr[2]), // Read-only address[2] input bit
.DPRA3(rd_addr[3]), // Read-only address[3] input bit
.DPRA4(rd_addr[4]), // Read-only address[4] input bit
.WCLK(clk), // Write clock input
.WE(wr_en) // Write enable input
);
end
endgenerate
`endif
endmodule // syncfifo
`elsif TARGET_CLEAN
defparam mem.DW=DW;
defparam mem.AW=AW;
memory_dp mem (
// Outputs
.rd_data (rd_data[DW-1:0]),
// Inputs
.wr_clk (clk),
.wr_en ({(DW/8){we_en}}),
.wr_addr (wr_addr[AW-1:0]),
.wr_data (wr_data[DW-1:0]),
.rd_clk (rd_clk),
.rd_en (rd_en),
.rd_addr (rd_addr[AW-1:0]));
`endif
endmodule // fifo_sync
// Local Variables:
// verilog-library-directories:(".")
// End:
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Fred Huettig <fred@adapteva.com>
Contributed by Andreas Olofsson <andreas@adapteva.com>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by

58
memory/hdl/memory_sp.v
View File

@ -1,65 +1,56 @@
/*###########################################################################
# Function: Single port memory wrapper
#
# To run without hardware platform dependancy use:
# `define TARGET_CLEAN"
############################################################################
*/
`define USE_MEM_MODEL
module memory_sp(/*AUTOARG*/
// Outputs
data_out,
// Inputs
clk, en, wen, addr, data_in
clk, en, wen, addr, din, dout
);
parameter AW = 14;
parameter DW = 32;
parameter WED = 4; //one per byte, how to parametrize
parameter WED = DW/8; //one per byte
parameter MD = 1<<AW;//memory depth
//memory interface
input clk; //write clock
input en; //memory enable
input [WED-1:0] wen; //write enable vector
input [AW-1:0] addr; //write address
input [DW-1:0] data_in; //write data
output reg [DW-1:0] data_out;//read output data
//////////////////////
//SIMPLE MEMORY MODEL
//////////////////////
`ifdef USE_MEM_MODEL
//write-port
input clk; //write clock
input en; //memory access
input [WED-1:0] wen; //write enable vector
input [AW-1:0] addr;//address
input [DW-1:0] din; //data input
input [DW-1:0] dout;//data output
`ifdef TARGET_CLEAN
reg [DW-1:0] ram [MD-1:0];
reg [DW-1:0] rd_data;
//read port
always @ (posedge clk)
if(en)
data_out[DW-1:0] <= ram[addr[AW-1:0]];
dout[DW-1:0] <= ram[addr[AW-1:0]];
//write port
generate
genvar i;
for (i = 0; i < 8; i = i+1) begin: gen_ram
always @(posedge clk)
for (i = 0; i < WED; i = i+1) begin: gen_ram
always @(posedge clk)
begin
if (wen[i])
ram[addr[AW-1:0]][(i+1)*8-1:i*8] <= data_in[(i+1)*8-1:i*8];
ram[addr[AW-1:0]][(i+1)*8-1:i*8] <= din[(i+1)*8-1:i*8];
end
end
endgenerate
`elsif TARGET_XILINX
//instantiate XILINX BRAM (based on parameter size)
`elsif TARGET_ALTERA
//instantiate ALTERA BRAM (based on paremeter size)
`endif
//////////////////////
//XILINX MEMORY
//////////////////////
//////////////////////
//CHIP MEMORY
//////////////////////
endmodule // memory_dp
@ -78,6 +69,7 @@ endmodule // memory_dp
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/