mirror of
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Making front page table links to README files
-Every folder should be more or less self contained -Hopefully one day this repo will look more like parallella-examples
This commit is contained in:
Andreas Olofsson
parent
8c350eed91
commit
f60f3515e6
61
README.md
61
README.md
@ -1,9 +1,9 @@
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=======
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# OH! Open hardware for Chips and FPGAs
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# OH! Open Hardware
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## CONTENT
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## Content
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1. [Philosophy](#philosophy)
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2. [Modules](#modules)
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@ -18,7 +18,7 @@
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----
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## PHILOSOPHY
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## Philosophy
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1. Make it work
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2. Make it simple
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@ -28,26 +28,25 @@
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## Modules
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| FOLDER | STATUS| DESCRIPTION |
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|--------------------------|-------|---------------------------------------|
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|[accelerator](accelerator)| FPGA | Accelerator tutorial |
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|[axi](axi) | FPGA | AXI master and slave interfaces |
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|[c2c](c2c) | HH | Protocol agnostic chip to chip link |
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|[chip](chip) | SI | Chip design reference flow |
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|[common](common) | SI | Library of basic components |
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|[elink](elink) | SI | Point to point LVDS link |
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|[emailbox](emailbox) | FPGA | Mailbox with interrupt output |
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|[emesh](emesh) | SI | Emesh interface utility circuits |
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|[emmu](emmu) | FPGA | Memory transaction translation unit |
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|[etrace](etrace) | HH | Logic Analyzer |
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|[gpio](gpio) | HH | General Purpose IO |
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|[mio](mio) | HH | Mini-IO: lightweight parallel link |
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|[pic](pic) | SI | Programmable interrupt controller |
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|[parallella](parallella) | FPGA | Parallella FPGA logic |
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|[risc-v](risc-v) | HH | RISC-V implementation |
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|[spi](spi) | HH | SPI master/slave |
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|[verilog](verilog) | HH | Verilog referenca material |
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|[xilibs](xilibs) | FPGA | Xilinx simulation models |
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| FOLDER | STATUS| DESCRIPTION |
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|------------------------------------|-------|--------------------------------|
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|[accelerator](accelerator/README.md)| FPGA | Accelerator tutorial |
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|[axi](axi/README.md) | FPGA | AXI master and slave interfaces|
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|[chip](chip/README.md) | SI | Chip design reference flow |
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|[common](common/README.md) | SI | Library of basic components |
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|[elink](elink/README.md) | SI | Point to point LVDS link |
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|[emailbox](emailbox/README.md) | FPGA | Mailbox with interrupt output |
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|[emesh](emesh/README.md) | SI | Emesh interface circuits |
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|[emmu](emmu/README.md) | FPGA | Memory translation unit |
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|[etrace](etrace/README.md) | HH | Logic Analyzer |
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|[gpio](gpio/README.md) | HH | General Purpose IO |
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|[mio](mio/README.md) | HH | Lightweight parallel link |
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|[pic](pic/README.md) | SI | Interrupt controller |
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|[parallella](parallella/README.md) | FPGA | Parallella FPGA logic |
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|[risc-v](risc-v/README.md) | HH | RISC-V implementation |
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|[spi](spi/README.md) | HH | SPI master/slave |
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|[verilog](verilog/README.md) | HH | Verilog referenca material |
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|[xilibs](xilibs/README.md) | FPGA | Xilinx simulation models |
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**NOTES:**
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* "SI"= Silicon validated
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@ -56,7 +55,7 @@
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----
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## HOW TO SIMULATE
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## How to simulate
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```sh
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./build.sh gpio/dv/dut_gpio.v # compile gpio testbench (example)
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----
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## HOW TO BUILD
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## How to build
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TBD
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----
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## DESIGN GUIDE
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## Design Guide
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* Separate control from the datapath
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* Separate configuration from design
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@ -101,7 +100,7 @@ TBD
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----
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# CODING GUIDE
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# Coding Guide
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* Max 80 chars per line
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* One input/output statement per line
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@ -155,7 +154,7 @@ TBD
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----
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## DOCUMENTATION GUIDE
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## Documentation Guide
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* Write docs in markdown
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* Specify which registers are reset
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@ -179,7 +178,7 @@ TBD
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----
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## DESIGN CHECKLIST
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## Design Checklist
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* Is the block datasheet complete and accurate?
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* Is there a user guide?
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@ -192,7 +191,7 @@ TBD
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----
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## RECOMMENDED READING
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## Recommended Reading
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* [Verilog Reference](verilog/verilog_reference.md)
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* [Glossary](chip/docs/glossary.md)
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* [Wavedrom](http://wavedrom.com/editor.html)
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* [FuseSoC](https://github.com/olofk/fusesoc)
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## LICENSE
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## License
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The OH! repository source code is licensed under the MIT license unless otherwise specified. See [LICENSE](LICENSE) for MIT copyright terms. Design specific licenses can be found in the folder root (eg: aes/LICENSE)
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----
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5
axi/README.md
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5
axi/README.md
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AXI : AXI master and slave interface
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====================================
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* axi_master
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* axi_slave
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2
emesh/README.md
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2
emesh/README.md
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EMESH: Various emesh interface circuits
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==========================================
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2
emmu/README.md
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2
emmu/README.md
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EMMU: Memory translation Unit
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=================================
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4
gpio/firmware/README.md
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4
gpio/firmware/README.md
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Driver layer for GPIO
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* Don't hard code, initialize correctly
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* uctions?
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48
gpio/firmware/gpio.c
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48
gpio/firmware/gpio.c
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#include "gpio.h"
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int gpio_init(int offset){
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}
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void gpio_mode(int dev, int pin, int val){
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}
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void gpio_write(int dev, int pin, int val){
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}
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void gpio_toggle(int dev, int pin){
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}
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int gpio_read(int dev, int pin){
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}
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void gpio_regwrite(int dev, const reg, uint64 val){
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}
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uint64 gpio_regread(int dev, const reg, uint64 val){
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}
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int gpio_spi_init(int dev, int pins){
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}
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char gpio_spi_transfer (int handle, char byte){
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int count;
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for (count = 8; count > 0; count--){
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//sclk=1;
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//mosi=byte & 0x80
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//byte=byte<<1
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//sclk=0
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//byte|=miso
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}
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return (byte);
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}
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42
gpio/firmware/gpio.h
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42
gpio/firmware/gpio.h
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#define GPIO_OFFSET 0
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#define GPIO_OEN 0
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#define GPIO_OUT 1
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#define GPIO_IEN 2
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#define GPIO_IN 3
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#define GPIO_OUTAND 4
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#define GPIO_OUTORR 5
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#define GPIO_OUTXOR 6
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#define GPIO_IMASK 7
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#include <stdint.h>
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// Provide pointer to GPIO module
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int gpio_init(int offset);
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// Set pin mode
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void gpio_mode(int dev, int pin, int val);
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// Write to a pin
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void gpio_write(int dev, int pin, int val);
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// Toggle a pin
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void gpio_toggle(int dev, int pin);
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// Read from a pin
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int gpio_read(int dev, int pin);
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// Write register
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void gpio_regwrite(int dev, const reg, uint64 val);
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// Read register
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uint64 gpio_regread(int dev, const reg, uint64 val);
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// Set up SPI
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int gpio_spi_init(int dev, int pins);
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// SPI transfer (byte)
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char gpio_spi_transfer(int handle, char data);
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13
gpio/firmware/gpio_example.c
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13
gpio/firmware/gpio_example.c
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#include "gpio.h"
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void main(){
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int led = 0;
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gpio_mode(led,GPIO_OUTPUT);
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while(1){
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gpio_write(led,1);
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usleep(1e6);
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gpio_write(led,0);
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usleep(1e6);
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}
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}
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2
parallella/README.md
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2
parallella/README.md
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PARALLELLA: FPGA logic for the parallella boards
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=================================================
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2
spi/README.md
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2
spi/README.md
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SPI: Serial Peripheral Interface
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=======================================
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2
verilog/README.md
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2
verilog/README.md
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VERILOG: Reference material
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================================================
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