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Upating packet2emesh with new format.

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-Moving sa0/sa1 in order to simplify
-With the new clean format there is no need for the split
This commit is contained in:
Andreas.Olofsson 2020-10-09 22:10:57 -04:00
parent 7c05557e6f
commit f6b9f6cad7
2 changed files with 61 additions and 110 deletions
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1
emesh/hdl/emesh2packet.v
View File

@ -76,6 +76,7 @@
* CMD[3] indicates
* Near/Far indicates whether to enable AW or AW/2 packet width
* All transactions are LSB aligned
* No return address for AW16 (point to point)
*
******************************************************************************/
module emesh2packet

170
emesh/hdl/packet2emesh.v
View File

@ -21,18 +21,17 @@ module packet2emesh
output [2*AW-1:0] data_in // write data
);
//Command always situated in lowest byte
assign cmd_in[7:0] = packet_in[7:0];
generate
//######################
// 16-Bit
// 16-Bit ("lite/apb like")
//######################
if(AW==16) begin : aw16
if(PW==40) begin : p40
assign cmd_in[7:0] = packet_in[7:0];
assign cmd_in[15:8] = 8'b0;
assign dstaddr_in[15:0] = packet_in[23:8];
assign srcaddr_in[15:0] = packet_in[39:24];
assign data_in[15:0] = {16'b0,packet_in[39:24]};
assign data_in[31:0] = {16'b0,packet_in[39:24]};
end
else begin: perror
initial
@ -43,68 +42,43 @@ module packet2emesh
// 32-Bit
//######################
if(AW==32) begin : aw32
if(PW==72) begin: p72
assign dstaddr_in[31:0] = packet_in[39:8];
assign srcaddr_in[31:0] = packet_in[71:40];
assign data_in[63:0] = {32'b0,packet_in[71:40]};
end
else if(PW==80) begin: p80
assign dstaddr_in[31:0] = packet_in[39:8];
assign srcaddr_in[31:0] = packet_in[71:40];
assign data_in[63:0] = {32'b0,packet_in[71:40]};
assign cmd_in[15:8] = packet_in[79:72];
end
else if(PW==104) begin: p104
assign dstaddr_in[31:0] = packet_in[39:8];
assign srcaddr_in[31:0] = packet_in[103:72];
assign data_in[63:0] = packet_in[103:40];
end
else if(PW==112) begin: p112
assign dstaddr_in[31:0] = packet_in[39:8];
assign srcaddr_in[31:0] = packet_in[103:72];
assign data_in[63:0] = packet_in[103:40];
assign cmd_in[15:8] = packet_in[111:104];
end
else begin: perror
initial
$display ("Combo not supported (PW=%ds AW==%ds)", PW,AW);
end
if(PW==80) begin: p80
assign cmd_in[15:0] = packet_in[15:0];
assign dstaddr_in[31:0] = packet_in[47:16];
assign srcaddr_in[31:0] = packet_in[79:48];
assign data_in[31:0] = packet_in[79:48];
assign data_in[63:32] = 32'b0;
end
else if(PW==112) begin: p112
assign cmd_in[15:0] = packet_in[15:0];
assign dstaddr_in[31:0] = packet_in[47:16];
assign srcaddr_in[31:0] = packet_in[79:48];
assign data_in[63:0] = packet_in[111:48];
end
else begin: perror
initial
$display ("Combo not supported (PW=%ds AW==%ds)", PW,AW);
end
end // block: aw32
//######################
// 64-Bit
//######################
if(AW==64) begin : aw64
if(PW==136) begin: p136
assign dstaddr_in[31:0] = packet_in[39:8];
assign dstaddr_in[63:32] = packet_in[135:104];
assign srcaddr_in[31:0] = packet_in[103:72];
assign srcaddr_in[63:32] = packet_in[71:40];
assign data_in[127:0] = {64'b0,packet_in[103:40]};
end
else if(PW==144) begin: p144
assign dstaddr_in[31:0] = packet_in[39:8];
assign dstaddr_in[63:32] = packet_in[135:104];
assign srcaddr_in[31:0] = packet_in[103:72];
assign srcaddr_in[63:32] = packet_in[71:40];
assign data_in[127:0] = {64'b0,packet_in[103:40]};
assign cmd_in[15:8] = packet_in[143:136];
end
else if(PW==200) begin: p200
assign dstaddr_in[31:0] = packet_in[39:8];
assign dstaddr_in[63:32] = packet_in[135:104];
assign srcaddr_in[31:0] = packet_in[103:72];
assign srcaddr_in[63:32] = packet_in[71:40];
assign data_in[63:0] = packet_in[103:40];
assign data_in[127:64] = packet_in[199:136];
if(PW==144) begin: p144
assign cmd_in[15:0] = packet_in[15:0];
assign dstaddr_in[31:0] = packet_in[47:16];
assign srcaddr_in[63:0] = packet_in[111:48];
assign data_in[127:0] = packet_in[111:48];
assign dstaddr_in[63:32] = packet_in[143:112];
assign data_in[127:64] = 64'b0;
end
else if(PW==208) begin: p208
assign dstaddr_in[31:0] = packet_in[39:8];
assign dstaddr_in[63:32] = packet_in[135:104];
assign srcaddr_in[31:0] = packet_in[103:72];
assign srcaddr_in[63:32] = packet_in[71:40];
assign data_in[63:0] = packet_in[103:40];
assign data_in[127:64] = packet_in[199:136];
assign cmd_in[15:8] = packet_in[207:200];
assign cmd_in[15:0] = packet_in[15:0];
assign dstaddr_in[31:0] = packet_in[47:16];
assign srcaddr_in[63:0] = packet_in[111:48];
assign data_in[63:0] = packet_in[111:48];
assign dstaddr_in[63:32] = packet_in[143:112];
assign data_in[127:64] = packet_in[207:144];
end
else begin: perror
initial
@ -115,59 +89,35 @@ module packet2emesh
// 128-Bit
//######################
if(AW==128) begin : aw128
if(PW==264) begin: p264
assign dstaddr_in[31:0] = packet_in[39:8];
assign dstaddr_in[63:32] = packet_in[135:104];
assign dstaddr_in[127:64] = packet_in[263:200];
assign srcaddr_in[31:0] = packet_in[103:72];
assign srcaddr_in[63:32] = packet_in[71:40];
assign srcaddr_in[127:64] = packet_in[199:136];
assign data_in[63:0] = packet_in[103:40];
assign data_in[127:64] = packet_in[199:136];
assign data_in[255:128] = 128'b0;
end
else if(PW==272) begin: p272
assign dstaddr_in[31:0] = packet_in[39:8];
assign dstaddr_in[63:32] = packet_in[135:104];
assign dstaddr_in[127:64] = packet_in[263:200];
assign srcaddr_in[31:0] = packet_in[103:72];
assign srcaddr_in[63:32] = packet_in[71:40];
assign srcaddr_in[127:64] = packet_in[199:136];
assign data_in[63:0] = packet_in[103:40];
assign data_in[127:64] = packet_in[199:136];
assign data_in[255:128] = 128'b0;
assign cmd_in[15:8] = packet_in[271:264];
end
else if(PW==392) begin: p392
assign dstaddr_in[31:0] = packet_in[39:8];
assign dstaddr_in[63:32] = packet_in[135:104];
assign dstaddr_in[127:64] = packet_in[263:200];
assign srcaddr_in[31:0] = packet_in[103:72];
assign srcaddr_in[63:32] = packet_in[71:40];
assign srcaddr_in[127:64] = packet_in[199:136];
assign data_in[63:0] = packet_in[103:40];
assign data_in[127:64] = packet_in[199:136];
assign data_in[255:128] = packet_in[391:264];
end
else if(PW==400) begin: p400
assign dstaddr_in[31:0] = packet_in[39:8];
assign dstaddr_in[63:32] = packet_in[135:104];
assign dstaddr_in[127:64] = packet_in[263:200];
assign srcaddr_in[31:0] = packet_in[103:72];
assign srcaddr_in[63:32] = packet_in[71:40];
assign srcaddr_in[127:64] = packet_in[199:136];
assign data_in[63:0] = packet_in[103:40];
assign data_in[127:64] = packet_in[199:136];
assign data_in[255:128] = packet_in[391:264];
assign cmd_in[15:8] = packet_in[399:392];
end
else begin: perror
initial
$display ("Combo not supported (PW=%ds AW==%ds)", PW,AW);
if(PW==272) begin: p272
assign cmd_in[15:0] = packet_in[15:0];
assign dstaddr_in[31:0] = packet_in[47:16];
assign srcaddr_in[63:0] = packet_in[111:48];
assign data_in[63:0] = packet_in[111:48];
assign dstaddr_in[63:32] = packet_in[143:112];
assign data_in[127:64] = packet_in[207:144];
assign srcaddr_in[127:64] = packet_in[207:144];
assign dstaddr_in[127:64] = packet_in[271:208];
assign data_in[255:128] = 128'b0;
end
else if(PW==400) begin: p400
assign cmd_in[15:0] = packet_in[15:0];
assign dstaddr_in[31:0] = packet_in[47:16];
assign srcaddr_in[63:0] = packet_in[111:48];
assign data_in[63:0] = packet_in[111:48];
assign dstaddr_in[63:32] = packet_in[143:112];
assign data_in[127:64] = packet_in[207:144];
assign srcaddr_in[127:64] = packet_in[207:144];
assign dstaddr_in[127:64] = packet_in[271:208];
assign data_in[255:128] = packet_in[399:272];
end
else begin: perror
initial
$display ("Combo not supported (PW=%ds AW==%ds)", PW,AW);
end
end // block: aw128
endgenerate
endmodule // packet2emesh