mirror of
https://github.com/aolofsson/oh.git
synced 2025-01-30 02:32:53 +08:00
Andreas Olofsson
commit
f753325686
@ -194,7 +194,6 @@ module axi_elink(/*AUTOARG*/
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wire rx_lclk; // From eclocks of eclocks.v
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wire rx_lclk_div4; // From eclocks of eclocks.v
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wire rx_lclk_pll; // From elink of elink.v
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wire rx_ref_clk; // From eclocks of eclocks.v
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wire rxrd_access; // From elink of elink.v
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wire [PW-1:0] rxrd_packet; // From elink of elink.v
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wire rxrd_wait; // From emaxi of emaxi.v
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@ -260,7 +259,6 @@ module axi_elink(/*AUTOARG*/
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.tx_lclk_div4 (tx_lclk_div4),
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.rx_lclk (rx_lclk),
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.rx_lclk_div4 (rx_lclk_div4),
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.rx_ref_clk (rx_ref_clk),
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.rxi_lclk_p (rxi_lclk_p),
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.rxi_lclk_n (rxi_lclk_n),
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.rxi_frame_p (rxi_frame_p),
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@ -293,7 +291,6 @@ module axi_elink(/*AUTOARG*/
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.tx_lclk_div4 (tx_lclk_div4),
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.rx_lclk (rx_lclk),
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.rx_lclk_div4 (rx_lclk_div4),
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.rx_ref_clk (rx_ref_clk),
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.e_cclk_p (e_cclk_p),
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.e_cclk_n (e_cclk_n),
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.elink_reset (elink_reset),
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@ -18,25 +18,18 @@
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module eclocks (/*AUTOARG*/
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// Outputs
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tx_lclk, tx_lclk90, tx_lclk_div4, rx_lclk, rx_lclk_div4,
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rx_ref_clk, e_cclk_p, e_cclk_n, elink_reset, e_resetb,
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e_cclk_p, e_cclk_n, elink_reset, e_resetb,
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// Inputs
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reset, elink_en, sys_clk, rx_clkin
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);
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parameter RCW = 4; // reset counter width
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parameter RCW = 8; // reset counter width
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//CCLK PLL
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parameter SYS_CLK_PERIOD = 10; // (2.5-100ns, set by system)
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parameter CCLK_VCO_MULT = 12; // 1200MHz
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parameter MMCM_VCO_MULT = 12; // 1200MHz
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parameter CCLK_DIVIDE = 2; // 600MHz
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//RX PLL
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parameter RXCLK_PERIOD = 3.3333333; // (2.5-100ns, set by system)
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parameter RXCLK_VCO_MULT = 4; // 1200MHz
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parameter RXCLK_DIVIDE = 4; // 300MHz
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parameter RXCLK_PHASE = 90; // sim setting, tune for FPGA
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parameter RXCLK_DIV4_PHASE = 22.5; // tune for FPGA!
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//TX (WITH RX FOR NOW...)
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parameter TXCLK_DIVIDE = 4; // 300MHz default
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@ -57,8 +50,7 @@ module eclocks (/*AUTOARG*/
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//RX Clocks
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output rx_lclk; // rx high speed clock for DDR IO
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output rx_lclk_div4; // rx slow clock for logic
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output rx_ref_clk; // clock for idelay element
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//Epiphany "free running" clock
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output e_cclk_p, e_cclk_n;
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@ -66,22 +58,48 @@ module eclocks (/*AUTOARG*/
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output elink_reset; // reset for elink logic & IO
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output e_resetb; // reset fpr Epiphany chip
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//############
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//# WIRES
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//############
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//CCLK
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wire cclk_reset;
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wire cclk_i;
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wire cclk_bufio;
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wire cclk_oddr;
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//Idelay controller
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wire idelay_reset;
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wire idelay_ready; //ignore this?
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wire idelay_ref_clk_i;
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wire idelay_ref_clk;
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//RX
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wire rx_lclk_i;
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wire rx_lclk_div4_i;
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//TX
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wire tx_lclk_i;
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wire tx_lclk90_i;
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wire tx_lckl_div4_i;
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//MMCM feedback
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wire mmcm_fb_in;
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wire mmcm_fb_out;
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//###########################
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// RESET STATE MACHINE
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//###########################
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wire cclk_locked;
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wire lclk_locked;
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reg [RCW:0] reset_counter = 'b0; //works b/c of free running counter!
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reg heartbeat;
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reg reset_in;
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reg reset_sync;
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reg pll_locked_sync;
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reg pll_locked;
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wire pll_reset;
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wire mmcm_reset;
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reg [2:0] reset_state;
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reg cclk_locked_reg;
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reg cclk_locked_sync;
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reg mmcm_locked_reg;
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reg mmcm_locked_sync;
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//wrap around counter that generates a 1 cycle heartbeat
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//free running counter...
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@ -94,17 +112,15 @@ module eclocks (/*AUTOARG*/
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//two clock synchronizer
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always @ (posedge sys_clk)
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begin
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cclk_locked_reg <= cclk_locked;
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cclk_locked_sync <= cclk_locked_reg;
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pll_locked_sync <= cclk_locked & lclk_locked;
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mmcm_locked_reg <= mmcm_locked;
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mmcm_locked_sync <= mmcm_locked_reg;
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reset_sync <= (reset | ~elink_en);
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reset_in <= reset_sync;
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pll_locked <= pll_locked_sync;
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end
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`define RESET_ALL 3'b000
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`define START_PLL 3'b001
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`define STOP_PLL 3'b010
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`define START_MMCM 3'b001
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`define STOP_CCLK 3'b010
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`define START_EPIPHANY 3'b011
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`define HOLD_IT 3'b100
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`define ACTIVE 3'b101
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@ -117,16 +133,16 @@ module eclocks (/*AUTOARG*/
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else if(heartbeat)
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case(reset_state[2:0])
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`RESET_ALL :
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reset_state[2:0] <= `START_PLL;
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`START_PLL :
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if(cclk_locked_sync)
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reset_state[2:0] <= `STOP_PLL;
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`STOP_PLL :
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reset_state[2:0] <= `START_MMCM;
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`START_MMCM :
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if(mmcm_locked_sync)
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reset_state[2:0] <= `STOP_CCLK;
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`STOP_CCLK :
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reset_state[2:0] <= `START_EPIPHANY;
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`START_EPIPHANY :
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reset_state[2:0] <= `HOLD_IT;
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`HOLD_IT :
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if(cclk_locked_sync)
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if(mmcm_locked_sync) //TODO: this is not necessary
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reset_state[2:0] <= `ACTIVE;
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`ACTIVE:
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reset_state[2:0] <= `ACTIVE; //stay there until nex reset
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@ -134,32 +150,29 @@ module eclocks (/*AUTOARG*/
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//reset PLL during 'reset' and during quiet time around reset edge
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assign pll_reset = (reset_state[2:0]==`RESET_ALL) |
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(reset_state[2:0]==`STOP_PLL) |
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(reset_state[2:0]==`START_EPIPHANY);
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assign mmcm_reset = (reset_state[2:0]==`RESET_ALL);
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assign idelay_reset = (reset_state[2:0]==`RESET_ALL) |
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(reset_state[2:0]==`START_MMCM);
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assign cclk_reset = (reset_state[2:0]==`STOP_CCLK) |
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(reset_state[2:0]==`START_EPIPHANY);
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assign e_resetb = (reset_state[2:0]==`START_EPIPHANY) |
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(reset_state[2:0]==`HOLD_IT) |
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(reset_state[2:0]==`ACTIVE);
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assign elink_reset = (reset_state[2:0]!=`ACTIVE);
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`ifdef TARGET_XILINX
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wire cclk_fb_in;
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wire cclk_fb_out;
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wire lclk_fb_in;
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wire lclk_fb_out;
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wire cclk;
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wire cclk_alt;
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//###########################
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// MMCM/PLL FOR CCLK AND TX
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//###########################
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MMCME2_ADV
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#(
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.BANDWIDTH("OPTIMIZED"),
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.CLKFBOUT_MULT_F(CCLK_VCO_MULT),
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.CLKFBOUT_MULT_F(MMCM_VCO_MULT),
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.CLKFBOUT_PHASE(0.0),
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.CLKIN1_PERIOD(SYS_CLK_PERIOD),
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.CLKOUT0_DIVIDE_F(CCLK_DIVIDE), // cclk
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@ -188,21 +201,21 @@ module eclocks (/*AUTOARG*/
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.STARTUP_WAIT("FALSE")
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) pll_cclk
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(
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.CLKOUT0(cclk),
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.CLKOUT0(cclk_i),
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.CLKOUT0B(),
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.CLKOUT1(tx_lclk),
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.CLKOUT1(tx_lclk_i),
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.CLKOUT1B(),
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.CLKOUT2(tx_lclk90),
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.CLKOUT2(tx_lclk90_i),
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.CLKOUT2B(),
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.CLKOUT3(tx_lclk_div4),
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.CLKOUT3(tx_lclk_div4_i),
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.CLKOUT3B(),
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.CLKOUT4(rx_ref_clk),
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.CLKOUT4(idelay_ref_clk_i),
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.CLKOUT5(),
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.CLKOUT6(),
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.PWRDWN(1'b0),
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.RST(pll_reset), //reset
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.CLKFBIN(cclk_fb_in),
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.CLKFBOUT(cclk_fb_out), //feedback clock
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.RST(mmcm_reset), //reset
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.CLKFBIN(mmcm_fb_in),
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.CLKFBOUT(mmcm_fb_out), //feedback clock
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.CLKIN1(sys_clk), //input clock
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.CLKIN2(1'b0),
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.CLKINSEL(1'b1),
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@ -213,7 +226,7 @@ module eclocks (/*AUTOARG*/
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.DWE(1'b0),
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.DRDY(),
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.DO(),
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.LOCKED(cclk_locked), //locked indicator
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.LOCKED(mmcm_locked), //locked indicator
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.PSCLK(1'b0),
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.PSEN(1'b0),
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.PSDONE(),
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@ -221,96 +234,69 @@ module eclocks (/*AUTOARG*/
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.CLKFBSTOPPED(),
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.CLKINSTOPPED()
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);
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BUFG pll_cclk_bufg(.I(cclk_fb_out), .O(cclk_fb_in));
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`ifdef EPHYCARD //Ephycard has cclk in a different region
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wire cclk_bufmr;
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wire cclk_bufio;
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wire cclk_oddr;
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//Tx clock buffers TODO: change to bufr? change port in MMCM in that case!!
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BUFG tx_lclk_bufg_i(.I(tx_lclk_i), .O(tx_lclk));
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BUFG tx_lclk_div4_bufg_i (.I(tx_lclk_div4_i), .O(tx_lclk_div4));
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BUFG tx_lclk90_bufg_i (.I(tx_lclk90_i), .O(tx_lclk90));
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//Idelay ref clock buffer
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BUFG idelay_ref_bufg_i(.I(idelay_ref_clk_i), .O(idelay_ref_clk));
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//Rx clock buffers
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BUFR rx_lclk_bufr_i(.I(rx_clkin), .O(rx_lclk));
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BUFR #(.BUFR_DIVIDE("4"))
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rx_lclk_div4_bufr_i
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(
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.I(rx_clkin),
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.O(rx_lclk_div4),
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.CE(1'b1),
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.CLR(1'b0));
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//Feedback buffer
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BUFR mmcm_fb_bufr_i(.I(mmcm_fb_out), .O(mmcm_fb_in));
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//###########################
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// CCLK
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//###########################
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//CCLK differential buffer
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OBUFDS cclk_obuf (.O (e_cclk_p),
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.OB (e_cclk_n),
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.I (cclk_oddr)
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);
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ODDR #(.DDR_CLK_EDGE ("SAME_EDGE"))
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oddr_lclk (
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.Q (cclk_oddr),
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.C (cclk_bufio),
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.CE (1'b1),
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.D1 (1'b1),
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.D2 (1'b0),
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.R (1'b0),
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.S (1'b0)
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);
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BUFIO bufio_cclk(.O(cclk_bufio), .I(cclk_bufmr));
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BUFMR bufmr_cclk(.O(cclk_bufmr), .I(cclk));
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`else
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OBUFDS cclk_obuf (.O (e_cclk_p),
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.OB (e_cclk_n),
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.I (cclk)
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);
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`endif
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//###########################
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// PLL RX CLOCK ALIGNMENT
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//###########################
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//CCLK oddr
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ODDR #(.DDR_CLK_EDGE ("SAME_EDGE"),
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.SRTYPE("ASYNC"))
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oddr_lclk (
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.Q (cclk_oddr),
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.C (cclk_bufio),
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.CE (1'b1),
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.D1 (1'b1),
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.D2 (1'b0),
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.R (1'b0),
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.S (1'b0));
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//CCLK bufio
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BUFIO bufio_cclk(.O(cclk_bufio), .I(cclk_i));
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PLLE2_ADV
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#(
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.BANDWIDTH("OPTIMIZED"),
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.CLKFBOUT_MULT(RXCLK_VCO_MULT),
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.CLKFBOUT_PHASE(0.0),
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.CLKIN1_PERIOD(RXCLK_PERIOD),
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.CLKOUT0_DIVIDE(CCLK_DIVIDE), // cclk
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.CLKOUT1_DIVIDE(TXCLK_DIVIDE), // tx_lclk
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.CLKOUT2_DIVIDE(TXCLK_DIVIDE), // tx_lclk90
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.CLKOUT3_DIVIDE(TXCLK_DIVIDE*4), // tx_lclk_div4
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.CLKOUT4_DIVIDE(RXCLK_DIVIDE), // rx_lclk
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.CLKOUT5_DIVIDE(RXCLK_DIVIDE*4), // rx_lclk_div4
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.CLKOUT0_DUTY_CYCLE(0.5),
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.CLKOUT1_DUTY_CYCLE(0.5),
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.CLKOUT2_DUTY_CYCLE(0.5),
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.CLKOUT3_DUTY_CYCLE(0.5),
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.CLKOUT4_DUTY_CYCLE(0.5),
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.CLKOUT5_DUTY_CYCLE(0.5),
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.CLKOUT0_PHASE(0.0),
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.CLKOUT1_PHASE(0.0),
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.CLKOUT2_PHASE(90.0),
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.CLKOUT3_PHASE(0.0),
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.CLKOUT4_PHASE(RXCLK_PHASE),
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.CLKOUT5_PHASE(RXCLK_DIV4_PHASE),
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.DIVCLK_DIVIDE(1.0),
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.REF_JITTER1(0.01),
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.STARTUP_WAIT("FALSE")
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) pll_elink
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(
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.CLKOUT0(cclk_alt),
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.CLKOUT1(),
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.CLKOUT2(),
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.CLKOUT3(),
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.CLKOUT4(rx_lclk),
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.CLKOUT5(rx_lclk_div4),
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.PWRDWN(1'b0),
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.RST(pll_reset),
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.CLKFBIN(lclk_fb_in),
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.CLKFBOUT(lclk_fb_out),
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.CLKIN1(rx_clkin),
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.CLKIN2(1'b0),
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.CLKINSEL(1'b1),
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.DADDR(7'b0),
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.DCLK(1'b0),
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.DEN(1'b0),
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.DI(16'b0),
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.DWE(1'b0),
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.DRDY(),
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.DO(),
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.LOCKED(lclk_locked)
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);
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BUFG pll_elink_bufg(.I(lclk_fb_out), .O(lclk_fb_in));
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//###########################
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// Idelay controller
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//###########################
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(* IODELAY_GROUP = "IDELAY_GROUP" *) // Group name for IDELAYCTRL
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IDELAYCTRL idelayctrl_inst
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(
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.RDY(idelay_ready), // check ready flag in reset sequence?
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.REFCLK(idelay_ref_clk),//200MHz clk (78ps tap delay)
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.RST(idelay_reset));
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`endif // `ifdef TARGET_XILINX
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@ -8,7 +8,7 @@ module elink(/*AUTOARG*/
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timeout,
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// Inputs
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reset, sys_clk, tx_lclk, tx_lclk90, tx_lclk_div4, rx_lclk,
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rx_lclk_div4, rx_ref_clk, rxi_lclk_p, rxi_lclk_n, rxi_frame_p,
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rx_lclk_div4, rxi_lclk_p, rxi_lclk_n, rxi_frame_p,
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rxi_frame_n, rxi_data_p, rxi_data_n, txi_wr_wait_p, txi_wr_wait_n,
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txi_rd_wait_p, txi_rd_wait_n, rxwr_wait, rxrd_wait, rxrr_wait,
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txwr_access, txwr_packet, txrd_access, txrd_packet, txrr_access,
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@ -31,7 +31,6 @@ module elink(/*AUTOARG*/
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input tx_lclk_div4; // slow tx clock for core logic
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input rx_lclk; // rx input clock tweaked by pll for IO
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input rx_lclk_div4; // slow clock for rx logic
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input rx_ref_clk; // 200MHz ref clock for rx idelay elements
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output rx_lclk_pll; // rx_lclk pass through input for pll
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/********************************/
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@ -199,7 +198,6 @@ module elink(/*AUTOARG*/
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.sys_clk (sys_clk),
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.rx_lclk (rx_lclk),
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.rx_lclk_div4 (rx_lclk_div4),
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.rx_ref_clk (rx_ref_clk),
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.rxi_lclk_p (rxi_lclk_p),
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.rxi_lclk_n (rxi_lclk_n),
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.rxi_frame_p (rxi_frame_p),
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@ -3,7 +3,6 @@
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//These constants are mutually exclusive
|
||||
`define TARGET_XILINX
|
||||
//`define EPHYCARD
|
||||
`define CFG_AW 32
|
||||
`define CFG_DW 32
|
||||
`define CFG_LW 8
|
||||
|
||||
@ -5,7 +5,7 @@ module erx (/*AUTOARG*/
|
||||
rxrr_access, rxrr_packet, erx_cfg_wait, timeout, mailbox_full,
|
||||
mailbox_not_empty,
|
||||
// Inputs
|
||||
erx_reset, sys_reset, sys_clk, rx_lclk, rx_lclk_div4, rx_ref_clk,
|
||||
erx_reset, sys_reset, sys_clk, rx_lclk, rx_lclk_div4,
|
||||
rxi_lclk_p, rxi_lclk_n, rxi_frame_p, rxi_frame_n, rxi_data_p,
|
||||
rxi_data_n, rxwr_wait, rxrd_wait, rxrr_wait, erx_cfg_access,
|
||||
erx_cfg_packet
|
||||
@ -26,7 +26,6 @@ module erx (/*AUTOARG*/
|
||||
input sys_clk; // system clock for rx fifos
|
||||
input rx_lclk; // fast clock for io
|
||||
input rx_lclk_div4; // slow clock for rest of logic
|
||||
input rx_ref_clk; // idelay reference clock
|
||||
output rx_lclk_pll; // clock output for pll
|
||||
|
||||
//FROM IO Pins
|
||||
@ -100,7 +99,6 @@ module erx (/*AUTOARG*/
|
||||
// Inputs
|
||||
.rx_lclk (rx_lclk),
|
||||
.rx_lclk_div4 (rx_lclk_div4),
|
||||
.rx_ref_clk (rx_ref_clk),
|
||||
.rxi_lclk_p (rxi_lclk_p),
|
||||
.rxi_lclk_n (rxi_lclk_n),
|
||||
.rxi_frame_p (rxi_frame_p),
|
||||
|
||||
@ -7,7 +7,7 @@ module erx_io (/*AUTOARG*/
|
||||
rx_lclk_pll, rxo_wr_wait_p, rxo_wr_wait_n, rxo_rd_wait_p,
|
||||
rxo_rd_wait_n, rx_access, rx_burst, rx_packet,
|
||||
// Inputs
|
||||
reset, rx_lclk, rx_lclk_div4, rx_ref_clk, rxi_lclk_p, rxi_lclk_n,
|
||||
reset, rx_lclk, rx_lclk_div4, rxi_lclk_p, rxi_lclk_n,
|
||||
rxi_frame_p, rxi_frame_n, rxi_data_p, rxi_data_n, rx_wr_wait,
|
||||
rx_rd_wait
|
||||
);
|
||||
@ -15,13 +15,16 @@ module erx_io (/*AUTOARG*/
|
||||
parameter IOSTD_ELINK = "LVDS_25";
|
||||
parameter PW = 104;
|
||||
|
||||
// Can we do this in a better way?
|
||||
parameter [8:0] RX_TAP_DELAY [8:0] = {10,11,10,10,10,11,11,11,11};
|
||||
|
||||
|
||||
//#########################
|
||||
//# reset, clocks
|
||||
//#########################
|
||||
input reset; // reset
|
||||
input rx_lclk; // fast I/O clock
|
||||
input rx_lclk_div4; // slow clock
|
||||
input rx_ref_clk; // idelay reference clock
|
||||
output rx_lclk_pll; // clock output for pll
|
||||
|
||||
//##########################
|
||||
@ -51,14 +54,15 @@ module erx_io (/*AUTOARG*/
|
||||
wire access_wide;
|
||||
reg valid_packet;
|
||||
wire [15:0] rx_word;
|
||||
wire rx_ref_clk_idlyctrl;
|
||||
|
||||
reg [15:0] rx_word_sync;
|
||||
|
||||
//############
|
||||
//# REGS
|
||||
//############
|
||||
reg [7:0] data_even_reg;
|
||||
reg [7:0] data_odd_reg;
|
||||
wire rx_frame;
|
||||
wire [1:0] rx_frame;
|
||||
reg [1:0] rx_frame_sync;
|
||||
wire rx_frame_old;
|
||||
reg [111:0] rx_sample;
|
||||
reg [6:0] rx_pointer;
|
||||
@ -71,54 +75,67 @@ module erx_io (/*AUTOARG*/
|
||||
wire rx_lclk_iddr;
|
||||
wire [8:0] rxi_delay_in;
|
||||
wire [8:0] rxi_delay_out;
|
||||
reg reset_sync;
|
||||
|
||||
//Reset sync
|
||||
always @ (posedge rx_lclk)
|
||||
reset_sync <= reset;
|
||||
|
||||
//#####################
|
||||
//#CREATE 112 BIT PACKET
|
||||
//#####################
|
||||
|
||||
//TODO: clean up!
|
||||
//write Pointer
|
||||
always @ (posedge rx_lclk)
|
||||
if (~rx_frame)
|
||||
rx_pointer[6:0] <= 7'b0000001; //new frame
|
||||
else if (rx_pointer[6])
|
||||
rx_pointer[6:0] <= 7'b0001000; //anticipate burst
|
||||
else if(rx_frame)
|
||||
rx_pointer[6:0] <= {rx_pointer[5:0],1'b0};//middle of frame
|
||||
|
||||
//convert to 112 bit packet
|
||||
always @ (posedge rx_lclk)
|
||||
if(rx_frame)
|
||||
if (~rx_frame_sync[1]) begin
|
||||
rx_pointer <= 3'b0; //new frame
|
||||
access <= 1'b0;
|
||||
end
|
||||
else if (rx_pointer != 3'd6 && (rx_frame_sync != 2'b00))
|
||||
begin
|
||||
if(rx_pointer[0])
|
||||
rx_sample[15:0] <= rx_word[15:0];
|
||||
if(rx_pointer[1])
|
||||
rx_sample[31:16] <= rx_word[15:0];
|
||||
if(rx_pointer[2])
|
||||
rx_sample[47:32] <= rx_word[15:0];
|
||||
if(rx_pointer[3])
|
||||
rx_sample[63:48] <= rx_word[15:0];
|
||||
if(rx_pointer[4])
|
||||
rx_sample[79:64] <= rx_word[15:0];
|
||||
if(rx_pointer[5])
|
||||
rx_sample[95:80] <= rx_word[15:0];
|
||||
if(rx_pointer[6])
|
||||
rx_sample[111:96] <= rx_word[15:0];
|
||||
rx_pointer <= rx_pointer + 1; //anticipate burst
|
||||
access <= 1'b0;
|
||||
end
|
||||
else begin
|
||||
rx_pointer <= 3'd3;//middle of frame
|
||||
access <= 1'b1;
|
||||
end
|
||||
|
||||
|
||||
// shift register for rx_word
|
||||
always @ (posedge rx_lclk)
|
||||
case (rx_frame_sync[1:0])
|
||||
2'b01 : begin
|
||||
rx_sample[111:8] <= rx_sample[103:0];
|
||||
rx_sample[7:0] <= rx_word_sync[7:0];
|
||||
end
|
||||
2'b10 : begin
|
||||
rx_sample[111:8] <= rx_sample[103:0];
|
||||
rx_sample[7:0] <= rx_word_sync[15:8];
|
||||
end
|
||||
2'b11 : begin
|
||||
rx_sample[111:16] <= rx_sample[95:0];
|
||||
rx_sample[15:0] <= rx_word_sync[15:0];
|
||||
end
|
||||
default :
|
||||
rx_sample <= rx_sample;
|
||||
endcase // case (rx_frame_sync[1:0])
|
||||
|
||||
|
||||
//#####################
|
||||
//#DATA VALID SIGNAL
|
||||
//####################
|
||||
|
||||
always @ (posedge rx_lclk)
|
||||
begin
|
||||
access <= rx_pointer[6];
|
||||
valid_packet <= access;//data pipeline
|
||||
end
|
||||
|
||||
reg burst_detect;
|
||||
always @ (posedge rx_lclk)
|
||||
if(access & rx_frame)
|
||||
if(access & rx_frame_sync[1])
|
||||
burst_detect <= 1'b1;
|
||||
else if(~rx_frame)
|
||||
else if(~rx_frame_sync)
|
||||
burst_detect <= 1'b0;
|
||||
|
||||
//###################################
|
||||
@ -131,44 +148,42 @@ module erx_io (/*AUTOARG*/
|
||||
begin
|
||||
//pipelin burst (delay by one frame)
|
||||
burst <= burst_detect;
|
||||
|
||||
//access
|
||||
rx_packet_lclk[0] <= rx_sample[40];
|
||||
rx_packet_lclk[0] <= rx_sample[64];
|
||||
|
||||
//write
|
||||
rx_packet_lclk[1] <= rx_sample[41];
|
||||
rx_packet_lclk[1] <= rx_sample[65];
|
||||
|
||||
//datamode
|
||||
rx_packet_lclk[3:2] <= rx_sample[43:42];
|
||||
rx_packet_lclk[3:2] <= rx_sample[67:66];
|
||||
|
||||
//ctrlmode
|
||||
rx_packet_lclk[7:4] <= rx_sample[15:12];
|
||||
rx_packet_lclk[7:4] <= rx_sample[103:100];
|
||||
|
||||
//dstaddr
|
||||
rx_packet_lclk[39:8] <= {rx_sample[11:8],
|
||||
rx_sample[23:16],
|
||||
rx_sample[31:24],
|
||||
rx_sample[39:32],
|
||||
rx_sample[47:44]};
|
||||
rx_packet_lclk[39:8] <= rx_sample[99:68];
|
||||
|
||||
//data
|
||||
rx_packet_lclk[71:40] <= {rx_sample[55:48],
|
||||
rx_sample[63:56],
|
||||
rx_sample[71:64],
|
||||
rx_sample[79:72]};
|
||||
rx_packet_lclk[71:40] <= rx_sample[63:32];
|
||||
|
||||
//srcaddr
|
||||
rx_packet_lclk[103:72]<= {rx_sample[87:80],
|
||||
rx_sample[95:88],
|
||||
rx_sample[103:96],
|
||||
rx_sample[111:104]
|
||||
};
|
||||
end
|
||||
rx_packet_lclk[103:72]<= rx_sample[31:0];
|
||||
end
|
||||
|
||||
//###################################
|
||||
//#SYNCHRONIZE TO SLOW CLK
|
||||
//###################################
|
||||
|
||||
//stretch access pulse to 4 cycles
|
||||
pulse_stretcher #(.DW(3)) ps0 (.out (access_wide),
|
||||
.in (valid_packet),
|
||||
.clk (rx_lclk),
|
||||
.reset (reset)
|
||||
);
|
||||
pulse_stretcher #(.DW(3))
|
||||
ps0 (
|
||||
.out(access_wide),
|
||||
.in(valid_packet),
|
||||
.clk(rx_lclk),
|
||||
.reset(reset_sync));
|
||||
|
||||
|
||||
always @ (posedge rx_lclk_div4)
|
||||
rx_access <= access_wide;
|
||||
|
||||
@ -236,7 +251,7 @@ module erx_io (/*AUTOARG*/
|
||||
//#RX CLOCK
|
||||
//###################################
|
||||
|
||||
BUFG bufg_lclk (.I(rxi_lclk), .O(rx_lclk_pll));
|
||||
assign rx_lclk_pll = rxi_lclk;
|
||||
|
||||
//###################################
|
||||
//#IDELAY CIRCUIT
|
||||
@ -244,22 +259,15 @@ module erx_io (/*AUTOARG*/
|
||||
|
||||
assign rxi_delay_in[8:0] ={rxi_frame,rxi_data[7:0]};
|
||||
|
||||
BUFG bufg_rx_ref_clk( .I(rx_ref_clk), .O(rx_ref_clk_idlyctrl));
|
||||
|
||||
//Do these need parameters?
|
||||
IDELAYCTRL idelayctrl_inst (.RDY(),
|
||||
.REFCLK(rx_ref_clk_idlyctrl),//200MHz clk (78ps tap delay)
|
||||
.RST(1'b0)
|
||||
);
|
||||
|
||||
genvar j;
|
||||
generate for(j=0; j<9; j=j+1)
|
||||
begin : gen_idelay
|
||||
begin : gen_idelay
|
||||
(* IODELAY_GROUP = "IDELAY_GROUP" *) // Group name for IDELAYCTRL
|
||||
IDELAYE2 #(.CINVCTRL_SEL("FALSE"),
|
||||
.DELAY_SRC("IDATAIN"),
|
||||
.HIGH_PERFORMANCE_MODE("FALSE"),
|
||||
.IDELAY_TYPE("FIXED"),
|
||||
.IDELAY_VALUE(14),
|
||||
.IDELAY_VALUE(RX_TAP_DELAY[j]),
|
||||
.PIPE_SEL("FALSE"),
|
||||
.REFCLK_FREQUENCY(200.0),
|
||||
.SIGNAL_PATTERN("DATA"))
|
||||
@ -283,36 +291,44 @@ module erx_io (/*AUTOARG*/
|
||||
//#############################
|
||||
//# IDDR SAMPLERS
|
||||
//#############################
|
||||
BUFIO bufio_lclk (.I(rxi_lclk),
|
||||
.O(rx_lclk_iddr));
|
||||
|
||||
//DATA
|
||||
genvar i;
|
||||
generate for(i=0; i<8; i=i+1)
|
||||
begin : gen_iddr
|
||||
IDDR #(.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"))
|
||||
IDDR #(.DDR_CLK_EDGE ("SAME_EDGE"), .SRTYPE("ASYNC"))
|
||||
iddr_data (
|
||||
.Q1 (rx_word[i]),
|
||||
.Q2 (rx_word[i+8]),
|
||||
.C (rx_lclk_iddr),
|
||||
.C (rx_lclk),
|
||||
.CE (1'b1),
|
||||
.D (rxi_delay_out[i]),
|
||||
.R (reset),
|
||||
.R (reset_sync),
|
||||
.S (1'b0)
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
//FRAME
|
||||
IDDR #(.DDR_CLK_EDGE ("SAME_EDGE_PIPELINED"))
|
||||
IDDR #(.DDR_CLK_EDGE ("SAME_EDGE"), .SRTYPE("ASYNC"))
|
||||
iddr_frame (
|
||||
.Q1 (),
|
||||
.Q2 (rx_frame),
|
||||
.C (rx_lclk_iddr),
|
||||
.Q1 (rx_frame[0]),
|
||||
.Q2 (rx_frame[1]),
|
||||
.C (rx_lclk),
|
||||
.CE (1'b1),
|
||||
.D (rxi_delay_out[8]),
|
||||
.R (reset),
|
||||
.R (reset_sync),
|
||||
.S (1'b0)
|
||||
);
|
||||
);
|
||||
|
||||
//Pipe stage
|
||||
always @ (posedge rx_lclk)
|
||||
rx_frame_sync <= rx_frame;
|
||||
|
||||
//Pipe stage
|
||||
always @ (posedge rx_lclk)
|
||||
rx_word_sync <= rx_word;
|
||||
|
||||
|
||||
endmodule // erx_io
|
||||
// Local Variables:
|
||||
|
||||
@ -1,4 +1,4 @@
|
||||
set oh_path "../.."
|
||||
set oh_path "../../../.."
|
||||
# Set the reference directory for source file relative paths (by default the value is script directory path)
|
||||
set origin_dir "."
|
||||
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>patrik</spirit:vendor>
|
||||
<spirit:vendor>Adapteva</spirit:vendor>
|
||||
<spirit:library>user</spirit:library>
|
||||
<spirit:name>axi_elink</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
@ -737,8 +737,8 @@
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>tx</spirit:name>
|
||||
<spirit:busType spirit:vendor="patrik" spirit:library="user" spirit:name="tx" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="patrik" spirit:library="user" spirit:name="tx_rtl" spirit:version="1.0"/>
|
||||
<spirit:busType spirit:vendor="Adapteva" spirit:library="user" spirit:name="tx" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="Adapteva" spirit:library="user" spirit:name="tx_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
@ -825,8 +825,8 @@
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>rx</spirit:name>
|
||||
<spirit:busType spirit:vendor="patrik" spirit:library="user" spirit:name="rx" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="patrik" spirit:library="user" spirit:name="rx_rtl" spirit:version="1.0"/>
|
||||
<spirit:busType spirit:vendor="Adapteva" spirit:library="user" spirit:name="rx" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="Adapteva" spirit:library="user" spirit:name="rx_rtl" spirit:version="1.0"/>
|
||||
<spirit:slave/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
@ -913,8 +913,8 @@
|
||||
</spirit:busInterface>
|
||||
<spirit:busInterface>
|
||||
<spirit:name>e_cclk</spirit:name>
|
||||
<spirit:busType spirit:vendor="patrik" spirit:library="user" spirit:name="e_cclk" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="patrik" spirit:library="user" spirit:name="e_cclk_rtl" spirit:version="1.0"/>
|
||||
<spirit:busType spirit:vendor="Adapteva" spirit:library="user" spirit:name="e_cclk" spirit:version="1.0"/>
|
||||
<spirit:abstractionType spirit:vendor="Adapteva" spirit:library="user" spirit:name="e_cclk_rtl" spirit:version="1.0"/>
|
||||
<spirit:master/>
|
||||
<spirit:portMaps>
|
||||
<spirit:portMap>
|
||||
@ -971,7 +971,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>ecc7b153</spirit:value>
|
||||
<spirit:value>17fb0d8a</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@ -989,7 +989,7 @@
|
||||
<spirit:parameters>
|
||||
<spirit:parameter>
|
||||
<spirit:name>viewChecksum</spirit:name>
|
||||
<spirit:value>ecc7b153</spirit:value>
|
||||
<spirit:value>17fb0d8a</spirit:value>
|
||||
</spirit:parameter>
|
||||
</spirit:parameters>
|
||||
</spirit:view>
|
||||
@ -2780,163 +2780,171 @@
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagesynthesis_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../xilibs/ip/fifo_async_104x16.xci</spirit:name>
|
||||
<spirit:name>../../../../xilibs/ip/fifo_async_104x16/fifo_async_104x16.xci</spirit:name>
|
||||
<spirit:userFileType>xci</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/elink_constants.v</spirit:name>
|
||||
<spirit:name>../../../../xilibs/ip/fifo_async_104x32/fifo_async_104x32.xci</spirit:name>
|
||||
<spirit:userFileType>xci</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../../../elink/hdl/elink_constants.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../memory/hdl/fifo_async.v</spirit:name>
|
||||
<spirit:name>../../../../memory/hdl/fifo_async.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../memory/hdl/memory_dp.v</spirit:name>
|
||||
<spirit:name>../../../../memory/hdl/memory_dp.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../emesh/hdl/packet2emesh.v</spirit:name>
|
||||
<spirit:name>../../../../emesh/hdl/packet2emesh.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../emesh/hdl/emesh2packet.v</spirit:name>
|
||||
<spirit:name>../../../../emesh/hdl/emesh2packet.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../common/hdl/arbiter_priority.v</spirit:name>
|
||||
<spirit:name>../../../../common/hdl/arbiter_priority.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../common/hdl/synchronizer.v</spirit:name>
|
||||
<spirit:name>../../../../common/hdl/synchronizer.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../emmu/hdl/emmu.v</spirit:name>
|
||||
<spirit:name>../../../../emmu/hdl/emmu.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../memory/hdl/fifo_cdc.v</spirit:name>
|
||||
<spirit:name>../../../../memory/hdl/fifo_cdc.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/elink_regmap.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/elink_regmap.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../emailbox/hdl/emailbox.v</spirit:name>
|
||||
<spirit:name>../../../../emailbox/hdl/emailbox.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../edma/hdl/edma.v</spirit:name>
|
||||
<spirit:name>../../../../edma/hdl/edma.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/erx_arbiter.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/erx_arbiter.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../common/hdl/pulse_stretcher.v</spirit:name>
|
||||
<spirit:name>../../../../common/hdl/pulse_stretcher.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/etx_protocol.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/etx_protocol.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/ecfg_if.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/ecfg_if.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/etx_remap.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/etx_remap.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/erx_protocol.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/erx_protocol.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/etx_arbiter.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/etx_arbiter.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/etx_cfg.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/etx_cfg.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/erx_cfg.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/erx_cfg.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/erx_remap.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/erx_remap.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/erx_io.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/erx_io.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/etx_io.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/etx_io.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/etx_fifo.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/etx_fifo.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/erx_core.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/erx_core.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/etx_core.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/etx_core.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/erx_fifo.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/erx_fifo.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/ecfg_elink.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/ecfg_elink.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/etx.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/etx.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/ereset.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/ereset.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/erx.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/erx.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../memory/hdl/fifo_sync.v</spirit:name>
|
||||
<spirit:name>../../../../memory/hdl/fifo_sync.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/elink.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/elink.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/emaxi.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/emaxi.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/esaxi.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/esaxi.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/eclocks.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/eclocks.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/axi_elink.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/axi_elink.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../xilibs/ip/fifo_async_104x16.xci</spirit:name>
|
||||
<spirit:name>../../../../xilibs/ip/fifo_async_104x16/fifo_async_104x16.xci</spirit:name>
|
||||
<spirit:userFileType>xci</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../../../xilibs/ip/fifo_async_104x32/fifo_async_104x32.xci</spirit:name>
|
||||
<spirit:userFileType>xci</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
@ -2953,163 +2961,171 @@
|
||||
<spirit:fileSet>
|
||||
<spirit:name>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:name>
|
||||
<spirit:file>
|
||||
<spirit:name>../../xilibs/ip/fifo_async_104x16.xci</spirit:name>
|
||||
<spirit:name>../../../../xilibs/ip/fifo_async_104x16/fifo_async_104x16.xci</spirit:name>
|
||||
<spirit:userFileType>xci</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/elink_constants.v</spirit:name>
|
||||
<spirit:name>../../../../xilibs/ip/fifo_async_104x32/fifo_async_104x32.xci</spirit:name>
|
||||
<spirit:userFileType>xci</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../../../elink/hdl/elink_constants.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../memory/hdl/fifo_async.v</spirit:name>
|
||||
<spirit:name>../../../../memory/hdl/fifo_async.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../memory/hdl/memory_dp.v</spirit:name>
|
||||
<spirit:name>../../../../memory/hdl/memory_dp.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../emesh/hdl/packet2emesh.v</spirit:name>
|
||||
<spirit:name>../../../../emesh/hdl/packet2emesh.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../emesh/hdl/emesh2packet.v</spirit:name>
|
||||
<spirit:name>../../../../emesh/hdl/emesh2packet.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../common/hdl/arbiter_priority.v</spirit:name>
|
||||
<spirit:name>../../../../common/hdl/arbiter_priority.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../common/hdl/synchronizer.v</spirit:name>
|
||||
<spirit:name>../../../../common/hdl/synchronizer.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../emmu/hdl/emmu.v</spirit:name>
|
||||
<spirit:name>../../../../emmu/hdl/emmu.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../memory/hdl/fifo_cdc.v</spirit:name>
|
||||
<spirit:name>../../../../memory/hdl/fifo_cdc.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/elink_regmap.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/elink_regmap.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../emailbox/hdl/emailbox.v</spirit:name>
|
||||
<spirit:name>../../../../emailbox/hdl/emailbox.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../edma/hdl/edma.v</spirit:name>
|
||||
<spirit:name>../../../../edma/hdl/edma.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/erx_arbiter.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/erx_arbiter.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../common/hdl/pulse_stretcher.v</spirit:name>
|
||||
<spirit:name>../../../../common/hdl/pulse_stretcher.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/etx_protocol.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/etx_protocol.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/ecfg_if.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/ecfg_if.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/etx_remap.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/etx_remap.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/erx_protocol.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/erx_protocol.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/etx_arbiter.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/etx_arbiter.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/etx_cfg.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/etx_cfg.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/erx_cfg.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/erx_cfg.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/erx_remap.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/erx_remap.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/erx_io.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/erx_io.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/etx_io.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/etx_io.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/etx_fifo.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/etx_fifo.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/erx_core.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/erx_core.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/etx_core.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/etx_core.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/erx_fifo.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/erx_fifo.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/ecfg_elink.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/ecfg_elink.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/etx.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/etx.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/ereset.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/ereset.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/erx.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/erx.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../memory/hdl/fifo_sync.v</spirit:name>
|
||||
<spirit:name>../../../../memory/hdl/fifo_sync.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/elink.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/elink.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/emaxi.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/emaxi.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/esaxi.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/esaxi.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/eclocks.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/eclocks.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../elink/hdl/axi_elink.v</spirit:name>
|
||||
<spirit:name>../../../../elink/hdl/axi_elink.v</spirit:name>
|
||||
<spirit:fileType>verilogSource</spirit:fileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../xilibs/ip/fifo_async_104x16.xci</spirit:name>
|
||||
<spirit:name>../../../../xilibs/ip/fifo_async_104x16/fifo_async_104x16.xci</spirit:name>
|
||||
<spirit:userFileType>xci</spirit:userFileType>
|
||||
</spirit:file>
|
||||
<spirit:file>
|
||||
<spirit:name>../../../../xilibs/ip/fifo_async_104x32/fifo_async_104x32.xci</spirit:name>
|
||||
<spirit:userFileType>xci</spirit:userFileType>
|
||||
</spirit:file>
|
||||
</spirit:fileSet>
|
||||
@ -3184,10 +3200,10 @@
|
||||
<xilinx:taxonomy>/UserIP</xilinx:taxonomy>
|
||||
</xilinx:taxonomies>
|
||||
<xilinx:displayName>axi_elink_v1_0</xilinx:displayName>
|
||||
<xilinx:coreRevision>4</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2015-06-30T21:35:37Z</xilinx:coreCreationDateTime>
|
||||
<xilinx:coreRevision>6</xilinx:coreRevision>
|
||||
<xilinx:coreCreationDateTime>2015-08-20T14:23:21Z</xilinx:coreCreationDateTime>
|
||||
<xilinx:tags>
|
||||
<xilinx:tag xilinx:name="patrik:user:axi_elink:1.0_ARCHIVE_LOCATION">../../projects/axi_elink</xilinx:tag>
|
||||
<xilinx:tag xilinx:name="Adapteva:user:axi_elink:1.0_ARCHIVE_LOCATION">E:/projects/ephycard</xilinx:tag>
|
||||
</xilinx:tags>
|
||||
</xilinx:coreExtensions>
|
||||
<xilinx:packagingInfo>
|
||||
@ -3195,7 +3211,7 @@
|
||||
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="dcb5c217"/>
|
||||
<xilinx:checksum xilinx:scope="addressSpaces" xilinx:value="bfa0be72"/>
|
||||
<xilinx:checksum xilinx:scope="memoryMaps" xilinx:value="78389c6b"/>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="4cada462"/>
|
||||
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="7baf097b"/>
|
||||
<xilinx:checksum xilinx:scope="ports" xilinx:value="b5e1b564"/>
|
||||
<xilinx:checksum xilinx:scope="hdlParameters" xilinx:value="85f55a50"/>
|
||||
<xilinx:checksum xilinx:scope="parameters" xilinx:value="5cb816ef"/>
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>patrik</spirit:vendor>
|
||||
<spirit:vendor>Adapteva</spirit:vendor>
|
||||
<spirit:library>user</spirit:library>
|
||||
<spirit:name>e_cclk</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
|
||||
@ -1,10 +1,10 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>patrik</spirit:vendor>
|
||||
<spirit:vendor>Adapteva</spirit:vendor>
|
||||
<spirit:library>user</spirit:library>
|
||||
<spirit:name>e_cclk_rtl</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busType spirit:vendor="patrik" spirit:library="user" spirit:name="e_cclk" spirit:version="1.0"/>
|
||||
<spirit:busType spirit:vendor="Adapteva" spirit:library="user" spirit:name="e_cclk" spirit:version="1.0"/>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>e_cclk_p</spirit:logicalName>
|
||||
|
||||
@ -1,8 +1,8 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>patrik</spirit:vendor>
|
||||
<spirit:vendor>Adapteva</spirit:vendor>
|
||||
<spirit:library>user</spirit:library>
|
||||
<spirit:name>e_cclk</spirit:name>
|
||||
<spirit:name>rx</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:directConnection>false</spirit:directConnection>
|
||||
<spirit:isAddressable>false</spirit:isAddressable>
|
||||
170
elink/projects/xilinx/axi_elink/interfaces/rx_rtl.xml
Executable file
170
elink/projects/xilinx/axi_elink/interfaces/rx_rtl.xml
Executable file
@ -0,0 +1,170 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>Adapteva</spirit:vendor>
|
||||
<spirit:library>user</spirit:library>
|
||||
<spirit:name>rx_rtl</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busType spirit:vendor="Adapteva" spirit:library="user" spirit:name="rx" spirit:version="1.0"/>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>rxi_data_n</spirit:logicalName>
|
||||
<spirit:description/>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>8</spirit:width>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>8</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>rxi_data_p</spirit:logicalName>
|
||||
<spirit:description/>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>8</spirit:width>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>8</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>rxi_frame_n</spirit:logicalName>
|
||||
<spirit:description/>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>rxi_frame_p</spirit:logicalName>
|
||||
<spirit:description/>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>rxi_lclk_n</spirit:logicalName>
|
||||
<spirit:description/>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>rxi_lclk_p</spirit:logicalName>
|
||||
<spirit:description/>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>rxo_wr_wait_p</spirit:logicalName>
|
||||
<spirit:description/>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>rxo_wr_wait_n</spirit:logicalName>
|
||||
<spirit:description/>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>rxo_rd_wait_p</spirit:logicalName>
|
||||
<spirit:description/>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>rxo_rd_wait_n</spirit:logicalName>
|
||||
<spirit:description/>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
</spirit:abstractionDefinition>
|
||||
11
elink/projects/xilinx/axi_elink/interfaces/tx.xml
Executable file
11
elink/projects/xilinx/axi_elink/interfaces/tx.xml
Executable file
@ -0,0 +1,11 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:busDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>Adapteva</spirit:vendor>
|
||||
<spirit:library>user</spirit:library>
|
||||
<spirit:name>tx</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:directConnection>false</spirit:directConnection>
|
||||
<spirit:isAddressable>false</spirit:isAddressable>
|
||||
<spirit:maxMasters>1</spirit:maxMasters>
|
||||
<spirit:maxSlaves>1</spirit:maxSlaves>
|
||||
</spirit:busDefinition>
|
||||
170
elink/projects/xilinx/axi_elink/interfaces/tx_rtl.xml
Executable file
170
elink/projects/xilinx/axi_elink/interfaces/tx_rtl.xml
Executable file
@ -0,0 +1,170 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>Adapteva</spirit:vendor>
|
||||
<spirit:library>user</spirit:library>
|
||||
<spirit:name>tx_rtl</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busType spirit:vendor="Adapteva" spirit:library="user" spirit:name="tx" spirit:version="1.0"/>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>txi_rd_wait_n</spirit:logicalName>
|
||||
<spirit:description/>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>txi_wr_wait_p</spirit:logicalName>
|
||||
<spirit:description/>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>txi_wr_wait_n</spirit:logicalName>
|
||||
<spirit:description/>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>txi_rd_wait_p</spirit:logicalName>
|
||||
<spirit:description/>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>txo_data_n</spirit:logicalName>
|
||||
<spirit:description/>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>8</spirit:width>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>8</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>txo_data_p</spirit:logicalName>
|
||||
<spirit:description/>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>8</spirit:width>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>8</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>txo_frame_n</spirit:logicalName>
|
||||
<spirit:description/>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>txo_frame_p</spirit:logicalName>
|
||||
<spirit:description/>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>txo_lclk_n</spirit:logicalName>
|
||||
<spirit:description/>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>txo_lclk_p</spirit:logicalName>
|
||||
<spirit:description/>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
</spirit:abstractionDefinition>
|
||||
115
elink/projects/xilinx/axi_elink/xgui/axi_elink_v1_0.tcl
Executable file
115
elink/projects/xilinx/axi_elink/xgui/axi_elink_v1_0.tcl
Executable file
@ -0,0 +1,115 @@
|
||||
# Definitional proc to organize widgets for parameters.
|
||||
proc init_gui { IPINST } {
|
||||
ipgui::add_param $IPINST -name "Component_Name"
|
||||
#Adding Page
|
||||
set Page_0 [ipgui::add_page $IPINST -name "Page 0"]
|
||||
ipgui::add_param $IPINST -name "AW" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "DW" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "ID" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "M_IDW" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "PW" -parent ${Page_0}
|
||||
ipgui::add_param $IPINST -name "S_IDW" -parent ${Page_0}
|
||||
|
||||
ipgui::add_param $IPINST -name "IOSTD_ELINK"
|
||||
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.AW { PARAM_VALUE.AW } {
|
||||
# Procedure called to update AW when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.AW { PARAM_VALUE.AW } {
|
||||
# Procedure called to validate AW
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.DW { PARAM_VALUE.DW } {
|
||||
# Procedure called to update DW when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.DW { PARAM_VALUE.DW } {
|
||||
# Procedure called to validate DW
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to update ID when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.ID { PARAM_VALUE.ID } {
|
||||
# Procedure called to validate ID
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.IOSTD_ELINK { PARAM_VALUE.IOSTD_ELINK } {
|
||||
# Procedure called to update IOSTD_ELINK when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.IOSTD_ELINK { PARAM_VALUE.IOSTD_ELINK } {
|
||||
# Procedure called to validate IOSTD_ELINK
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.M_IDW { PARAM_VALUE.M_IDW } {
|
||||
# Procedure called to update M_IDW when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.M_IDW { PARAM_VALUE.M_IDW } {
|
||||
# Procedure called to validate M_IDW
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.PW { PARAM_VALUE.PW } {
|
||||
# Procedure called to update PW when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.PW { PARAM_VALUE.PW } {
|
||||
# Procedure called to validate PW
|
||||
return true
|
||||
}
|
||||
|
||||
proc update_PARAM_VALUE.S_IDW { PARAM_VALUE.S_IDW } {
|
||||
# Procedure called to update S_IDW when any of the dependent parameters in the arguments change
|
||||
}
|
||||
|
||||
proc validate_PARAM_VALUE.S_IDW { PARAM_VALUE.S_IDW } {
|
||||
# Procedure called to validate S_IDW
|
||||
return true
|
||||
}
|
||||
|
||||
|
||||
proc update_MODELPARAM_VALUE.AW { MODELPARAM_VALUE.AW PARAM_VALUE.AW } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.AW}] ${MODELPARAM_VALUE.AW}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.DW { MODELPARAM_VALUE.DW PARAM_VALUE.DW } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.DW}] ${MODELPARAM_VALUE.DW}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.PW { MODELPARAM_VALUE.PW PARAM_VALUE.PW } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.PW}] ${MODELPARAM_VALUE.PW}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.ID { MODELPARAM_VALUE.ID PARAM_VALUE.ID } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.ID}] ${MODELPARAM_VALUE.ID}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.M_IDW { MODELPARAM_VALUE.M_IDW PARAM_VALUE.M_IDW } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.M_IDW}] ${MODELPARAM_VALUE.M_IDW}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.S_IDW { MODELPARAM_VALUE.S_IDW PARAM_VALUE.S_IDW } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.S_IDW}] ${MODELPARAM_VALUE.S_IDW}
|
||||
}
|
||||
|
||||
proc update_MODELPARAM_VALUE.IOSTD_ELINK { MODELPARAM_VALUE.IOSTD_ELINK PARAM_VALUE.IOSTD_ELINK } {
|
||||
# Procedure called to set VHDL generic/Verilog parameter value(s) based on TCL parameter value
|
||||
set_property value [get_property value ${PARAM_VALUE.IOSTD_ELINK}] ${MODELPARAM_VALUE.IOSTD_ELINK}
|
||||
}
|
||||
|
||||
@ -1,358 +0,0 @@
|
||||
set oh_path "../.."
|
||||
# Set the reference directory for source file relative paths (by default the value is script directory path)
|
||||
set origin_dir "."
|
||||
|
||||
# Set the directory path for the original project from where this script was exported
|
||||
set orig_proj_dir "[file normalize "$origin_dir"]"
|
||||
|
||||
# Create project
|
||||
create_project axi_elink_v1_0 .
|
||||
|
||||
# Set the directory path for the new project
|
||||
set proj_dir [get_property directory [current_project]]
|
||||
|
||||
# Set project properties
|
||||
set obj [get_projects axi_elink_v1_0]
|
||||
set_property "default_lib" "xil_defaultlib" $obj
|
||||
set_property "part" "xc7z030sbg485-1" $obj
|
||||
set_property "simulator_language" "Mixed" $obj
|
||||
|
||||
# Create 'sources_1' fileset (if not found)
|
||||
if {[string equal [get_filesets -quiet sources_1] ""]} {
|
||||
create_fileset -srcset sources_1
|
||||
}
|
||||
|
||||
# Set IP repository paths
|
||||
set obj [get_filesets sources_1]
|
||||
set_property "ip_repo_paths" "[file normalize "$origin_dir"] [file normalize "$origin_dir"]" $obj
|
||||
|
||||
# Rebuild user ip_repo's index before adding any source files
|
||||
update_ip_catalog -rebuild
|
||||
|
||||
# Set 'sources_1' fileset object
|
||||
set obj [get_filesets sources_1]
|
||||
set files [list \
|
||||
"[file normalize "$oh_path/xilibs/ip/fifo_async_104x16/fifo_async_104x16.xci"]"\
|
||||
"[file normalize "$oh_path/xilibs/ip/fifo_async_104x32/fifo_async_104x32.xci"]"\
|
||||
"[file normalize "$oh_path/memory/hdl/fifo_async.v"]"\
|
||||
"[file normalize "$oh_path/memory/hdl/memory_dp.v"]"\
|
||||
"[file normalize "$oh_path/emesh/hdl/packet2emesh.v"]"\
|
||||
"[file normalize "$oh_path/emesh/hdl/emesh2packet.v"]"\
|
||||
"[file normalize "$oh_path/common/hdl/arbiter_priority.v"]"\
|
||||
"[file normalize "$oh_path/common/hdl/synchronizer.v"]"\
|
||||
"[file normalize "$oh_path/emmu/hdl/emmu.v"]"\
|
||||
"[file normalize "$oh_path/memory/hdl/fifo_cdc.v"]"\
|
||||
"[file normalize "$oh_path/emailbox/hdl/emailbox.v"]"\
|
||||
"[file normalize "$oh_path/edma/hdl/edma.v"]"\
|
||||
"[file normalize "$oh_path/elink/hdl/elink_regmap.v"]"\
|
||||
"[file normalize "$oh_path/elink/hdl/erx_arbiter.v"]"\
|
||||
"[file normalize "$oh_path/common/hdl/pulse_stretcher.v"]"\
|
||||
"[file normalize "$oh_path/elink/hdl/etx_protocol.v"]"\
|
||||
"[file normalize "$oh_path/elink/hdl/ecfg_if.v"]"\
|
||||
"[file normalize "$oh_path/elink/hdl/etx_remap.v"]"\
|
||||
"[file normalize "$oh_path/elink/hdl/elink_constants.v"]"\
|
||||
"[file normalize "$oh_path/elink/hdl/erx_protocol.v"]"\
|
||||
"[file normalize "$oh_path/elink/hdl/etx_arbiter.v"]"\
|
||||
"[file normalize "$oh_path/elink/hdl/etx_cfg.v"]"\
|
||||
"[file normalize "$oh_path/elink/hdl/erx_cfg.v"]"\
|
||||
"[file normalize "$oh_path/elink/hdl/erx_remap.v"]"\
|
||||
"[file normalize "$oh_path/elink/hdl/erx_io.v"]"\
|
||||
"[file normalize "$oh_path/elink/hdl/etx_io.v"]"\
|
||||
"[file normalize "$oh_path/elink/hdl/etx_fifo.v"]"\
|
||||
"[file normalize "$oh_path/elink/hdl/erx_core.v"]"\
|
||||
"[file normalize "$oh_path/elink/hdl/etx_core.v"]"\
|
||||
"[file normalize "$oh_path/elink/hdl/erx_fifo.v"]"\
|
||||
"[file normalize "$oh_path/elink/hdl/ecfg_elink.v"]"\
|
||||
"[file normalize "$oh_path/elink/hdl/etx.v"]"\
|
||||
"[file normalize "$oh_path/elink/hdl/ereset.v"]"\
|
||||
"[file normalize "$oh_path/elink/hdl/erx.v"]"\
|
||||
"[file normalize "$oh_path/memory/hdl/fifo_sync.v"]"\
|
||||
"[file normalize "$oh_path/elink/hdl/elink.v"]"\
|
||||
"[file normalize "$oh_path/elink/hdl/emaxi.v"]"\
|
||||
"[file normalize "$oh_path/elink/hdl/esaxi.v"]"\
|
||||
"[file normalize "$oh_path/elink/hdl/eclocks.v"]"\
|
||||
"[file normalize "$oh_path/elink/hdl/axi_elink.v"]"\
|
||||
"[file normalize "$origin_dir/component.xml"]"\
|
||||
]
|
||||
add_files -norecurse -fileset $obj $files
|
||||
|
||||
# Set 'sources_1' fileset file properties for remote files
|
||||
set file "$oh_path/xilibs/ip/fifo_async_104x16/fifo_async_104x16.xci"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
if { ![get_property "is_locked" $file_obj] } {
|
||||
set_property "synth_checkpoint_mode" "Singular" $file_obj
|
||||
}
|
||||
set_property "used_in_implementation" "0" $file_obj
|
||||
|
||||
# Set 'sources_1' fileset file properties for remote files
|
||||
set file "$oh_path/xilibs/ip/fifo_async_104x32/fifo_async_104x32.xci"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
if { ![get_property "is_locked" $file_obj] } {
|
||||
set_property "synth_checkpoint_mode" "Singular" $file_obj
|
||||
}
|
||||
set_property "used_in_implementation" "0" $file_obj
|
||||
|
||||
|
||||
|
||||
set file "$oh_path/memory/hdl/fifo_async.v"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property "used_in_implementation" "0" $file_obj
|
||||
|
||||
set file "$oh_path/memory/hdl/memory_dp.v"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property "used_in_implementation" "0" $file_obj
|
||||
|
||||
set file "$oh_path/emesh/hdl/packet2emesh.v"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property "used_in_implementation" "0" $file_obj
|
||||
|
||||
set file "$oh_path/emesh/hdl/emesh2packet.v"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property "used_in_implementation" "0" $file_obj
|
||||
|
||||
set file "$oh_path/common/hdl/arbiter_priority.v"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property "used_in_implementation" "0" $file_obj
|
||||
|
||||
set file "$oh_path/common/hdl/synchronizer.v"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property "used_in_implementation" "0" $file_obj
|
||||
|
||||
set file "$oh_path/emmu/hdl/emmu.v"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property "used_in_implementation" "0" $file_obj
|
||||
|
||||
set file "$oh_path/memory/hdl/fifo_cdc.v"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property "used_in_implementation" "0" $file_obj
|
||||
|
||||
set file "$oh_path/emailbox/hdl/emailbox.v"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property "used_in_implementation" "0" $file_obj
|
||||
|
||||
set file "$oh_path/edma/hdl/edma.v"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property "used_in_implementation" "0" $file_obj
|
||||
|
||||
set file "$oh_path/elink/hdl/elink_regmap.v"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property "used_in_implementation" "0" $file_obj
|
||||
|
||||
set file "$oh_path/elink/hdl/erx_arbiter.v"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property "used_in_implementation" "0" $file_obj
|
||||
|
||||
set file "$oh_path/common/hdl/pulse_stretcher.v"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property "used_in_implementation" "0" $file_obj
|
||||
|
||||
set file "$oh_path/elink/hdl/etx_protocol.v"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property "used_in_implementation" "0" $file_obj
|
||||
|
||||
set file "$oh_path/elink/hdl/ecfg_if.v"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property "used_in_implementation" "0" $file_obj
|
||||
|
||||
set file "$oh_path/elink/hdl/etx_remap.v"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property "used_in_implementation" "0" $file_obj
|
||||
|
||||
set file "$oh_path/elink/hdl/elink_constants.v"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property "used_in_implementation" "0" $file_obj
|
||||
|
||||
set file "$oh_path/elink/hdl/erx_protocol.v"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property "used_in_implementation" "0" $file_obj
|
||||
|
||||
set file "$oh_path/elink/hdl/etx_arbiter.v"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property "used_in_implementation" "0" $file_obj
|
||||
|
||||
set file "$oh_path/elink/hdl/etx_cfg.v"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property "used_in_implementation" "0" $file_obj
|
||||
|
||||
set file "$oh_path/elink/hdl/erx_cfg.v"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property "used_in_implementation" "0" $file_obj
|
||||
|
||||
set file "$oh_path/elink/hdl/erx_remap.v"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property "used_in_implementation" "0" $file_obj
|
||||
|
||||
set file "$oh_path/elink/hdl/erx_io.v"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property "used_in_implementation" "0" $file_obj
|
||||
|
||||
set file "$oh_path/elink/hdl/etx_io.v"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property "used_in_implementation" "0" $file_obj
|
||||
|
||||
set file "$oh_path/elink/hdl/etx_fifo.v"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property "used_in_implementation" "0" $file_obj
|
||||
|
||||
set file "$oh_path/elink/hdl/erx_core.v"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property "used_in_implementation" "0" $file_obj
|
||||
|
||||
set file "$oh_path/elink/hdl/etx_core.v"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property "used_in_implementation" "0" $file_obj
|
||||
|
||||
set file "$oh_path/elink/hdl/erx_fifo.v"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property "used_in_implementation" "0" $file_obj
|
||||
|
||||
set file "$oh_path/elink/hdl/ecfg_elink.v"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property "used_in_implementation" "0" $file_obj
|
||||
|
||||
set file "$oh_path/elink/hdl/etx.v"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property "used_in_implementation" "0" $file_obj
|
||||
|
||||
set file "$oh_path/elink/hdl/ereset.v"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property "used_in_implementation" "0" $file_obj
|
||||
|
||||
set file "$oh_path/elink/hdl/erx.v"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property "used_in_implementation" "0" $file_obj
|
||||
|
||||
set file "$oh_path/memory/hdl/fifo_sync.v"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property "used_in_implementation" "0" $file_obj
|
||||
|
||||
set file "$oh_path/elink/hdl/elink.v"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property "used_in_implementation" "0" $file_obj
|
||||
|
||||
set file "$oh_path/elink/hdl/emaxi.v"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property "used_in_implementation" "0" $file_obj
|
||||
|
||||
set file "$oh_path/elink/hdl/esaxi.v"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property "used_in_implementation" "0" $file_obj
|
||||
|
||||
set file "$oh_path/elink/hdl/eclocks.v"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property "used_in_implementation" "0" $file_obj
|
||||
|
||||
set file "$oh_path/elink/hdl/axi_elink.v"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property "used_in_implementation" "0" $file_obj
|
||||
|
||||
set file "$origin_dir/component.xml"
|
||||
set file [file normalize $file]
|
||||
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
|
||||
set_property "file_type" "IP-XACT" $file_obj
|
||||
|
||||
|
||||
# Set 'sources_1' fileset file properties for local files
|
||||
# None
|
||||
|
||||
# Set 'sources_1' fileset properties
|
||||
set obj [get_filesets sources_1]
|
||||
set_property "top" "axi_elink" $obj
|
||||
|
||||
# Create 'constrs_1' fileset (if not found)
|
||||
if {[string equal [get_filesets -quiet constrs_1] ""]} {
|
||||
create_fileset -constrset constrs_1
|
||||
}
|
||||
|
||||
# Set 'constrs_1' fileset object
|
||||
set obj [get_filesets constrs_1]
|
||||
|
||||
# Empty (no sources present)
|
||||
|
||||
# Set 'constrs_1' fileset properties
|
||||
set obj [get_filesets constrs_1]
|
||||
|
||||
# Create 'sim_1' fileset (if not found)
|
||||
if {[string equal [get_filesets -quiet sim_1] ""]} {
|
||||
create_fileset -simset sim_1
|
||||
}
|
||||
|
||||
# Set 'sim_1' fileset object
|
||||
set obj [get_filesets sim_1]
|
||||
# Empty (no sources present)
|
||||
|
||||
# Set 'sim_1' fileset properties
|
||||
set obj [get_filesets sim_1]
|
||||
set_property "top" "axi_elink" $obj
|
||||
set_property "xelab.nosort" "1" $obj
|
||||
set_property "xelab.unifast" "" $obj
|
||||
|
||||
# Create 'synth_1' run (if not found)
|
||||
if {[string equal [get_runs -quiet synth_1] ""]} {
|
||||
create_run -name synth_1 -part xc7z030sbg485-1 -flow {Vivado Synthesis 2015} -strategy "Vivado Synthesis Defaults" -constrset constrs_1
|
||||
} else {
|
||||
set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]
|
||||
set_property flow "Vivado Synthesis 2015" [get_runs synth_1]
|
||||
}
|
||||
set obj [get_runs synth_1]
|
||||
set_property "part" "xc7z030sbg485-1" $obj
|
||||
|
||||
# set the current synth run
|
||||
current_run -synthesis [get_runs synth_1]
|
||||
|
||||
# Create 'impl_1' run (if not found)
|
||||
if {[string equal [get_runs -quiet impl_1] ""]} {
|
||||
create_run -name impl_1 -part xc7z030sbg485-1 -flow {Vivado Implementation 2015} -strategy "Vivado Implementation Defaults" -constrset constrs_1 -parent_run synth_1
|
||||
} else {
|
||||
set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
|
||||
set_property flow "Vivado Implementation 2015" [get_runs impl_1]
|
||||
}
|
||||
set obj [get_runs impl_1]
|
||||
set_property "part" "xc7z030sbg485-1" $obj
|
||||
set_property "steps.write_bitstream.args.readback_file" "0" $obj
|
||||
set_property "steps.write_bitstream.args.verbose" "0" $obj
|
||||
|
||||
# set the current impl run
|
||||
current_run -implementation [get_runs impl_1]
|
||||
|
||||
puts "INFO: Project created:axi_elink_v1_0_project"
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,42 +0,0 @@
|
||||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<spirit:abstractionDefinition xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
||||
<spirit:vendor>patrik</spirit:vendor>
|
||||
<spirit:library>user</spirit:library>
|
||||
<spirit:name>e_cclk_rtl</spirit:name>
|
||||
<spirit:version>1.0</spirit:version>
|
||||
<spirit:busType spirit:vendor="patrik" spirit:library="user" spirit:name="e_cclk" spirit:version="1.0"/>
|
||||
<spirit:ports>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>e_cclk_p</spirit:logicalName>
|
||||
<spirit:description/>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
<spirit:port>
|
||||
<spirit:logicalName>e_cclk_n</spirit:logicalName>
|
||||
<spirit:description/>
|
||||
<spirit:wire>
|
||||
<spirit:onMaster>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>out</spirit:direction>
|
||||
</spirit:onMaster>
|
||||
<spirit:onSlave>
|
||||
<spirit:presence>required</spirit:presence>
|
||||
<spirit:width>1</spirit:width>
|
||||
<spirit:direction>in</spirit:direction>
|
||||
</spirit:onSlave>
|
||||
</spirit:wire>
|
||||
</spirit:port>
|
||||
</spirit:ports>
|
||||
</spirit:abstractionDefinition>
|
||||
Loading…
x
Reference in New Issue
Block a user