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Fixing spi controller
- Manually merging work from @olajep in PR #85 (too far out of sync) - Fixing issue with lsbfirst logic - Adding logic for manual control of slave select - Fixing status register for polling reads - Still a timing/glitch issue on mosi, fix it later...
This commit is contained in:
Andreas Olofsson
parent
f4a74b462f
commit
f7ce7b800c
@ -34,6 +34,11 @@ module spi #( parameter AW = 32, // address width
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output s_miso // slave output
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);
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//1. set manual_CS mode
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//2. assert ss (0000)
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//4. write to tx fifo
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//6. deassert ss (1111)
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//###############
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//# LOCAL WIRES
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//###############
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@ -47,10 +47,12 @@ module spi_master # ( parameter DEPTH = 32, // fifo depth
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wire fifo_read; // From spi_master_io of spi_master_io.v
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wire fifo_wait; // From spi_master_fifo of spi_master_fifo.v
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wire lsbfirst; // From spi_master_regs of spi_master_regs.v
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wire manual_mode; // From spi_master_regs of spi_master_regs.v
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wire rx_access; // From spi_master_io of spi_master_io.v
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wire [63:0] rx_data; // From spi_master_io of spi_master_io.v
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wire send_data; // From spi_master_regs of spi_master_regs.v
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wire spi_en; // From spi_master_regs of spi_master_regs.v
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wire [1:0] spi_state; // From spi_master_io of spi_master_io.v
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wire [2:0] spi_state; // From spi_master_io of spi_master_io.v
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// End of automatics
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//#####################################################
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@ -65,6 +67,8 @@ module spi_master # ( parameter DEPTH = 32, // fifo depth
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.cpha (cpha),
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.lsbfirst (lsbfirst),
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.spi_en (spi_en),
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.manual_mode (manual_mode),
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.send_data (send_data),
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.clkdiv_reg (clkdiv_reg[7:0]),
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.wait_out (wait_out),
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.access_out (access_out),
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@ -75,7 +79,7 @@ module spi_master # ( parameter DEPTH = 32, // fifo depth
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.hw_en (hw_en),
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.rx_data (rx_data[63:0]),
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.rx_access (rx_access),
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.spi_state (spi_state[1:0]),
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.spi_state (spi_state[2:0]),
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.fifo_prog_full (fifo_prog_full),
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.fifo_wait (fifo_wait),
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.access_in (access_in),
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@ -116,7 +120,7 @@ module spi_master # ( parameter DEPTH = 32, // fifo depth
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spi_master_io
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spi_master_io (/*AUTOINST*/
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// Outputs
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.spi_state (spi_state[1:0]),
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.spi_state (spi_state[2:0]),
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.fifo_read (fifo_read),
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.rx_data (rx_data[63:0]),
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.rx_access (rx_access),
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@ -129,6 +133,8 @@ module spi_master # ( parameter DEPTH = 32, // fifo depth
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.cpol (cpol),
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.cpha (cpha),
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.lsbfirst (lsbfirst),
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.manual_mode (manual_mode),
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.send_data (send_data),
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.clkdiv_reg (clkdiv_reg[7:0]),
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.fifo_dout (fifo_dout[7:0]),
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.fifo_empty (fifo_empty),
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@ -12,8 +12,10 @@ module spi_master_io
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input cpol, // cpol
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input cpha, // cpha
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input lsbfirst, // send lsbfirst
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input manual_mode,// sets automatic ss mode
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input send_data, // controls ss in manual ss mode
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input [7:0] clkdiv_reg, // baudrate
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output reg [1:0] spi_state, // current spi tx state
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output reg [2:0] spi_state, // current spi tx state
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// data to transmit
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input [7:0] fifo_dout, // data payload
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input fifo_empty, //
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@ -33,6 +35,8 @@ module spi_master_io
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//###############
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reg fifo_empty_reg;
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reg load_byte;
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wire rx_access;
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reg ss_reg;
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wire [7:0] data_out;
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wire [15:0] clkphase0;
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wire period_match;
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@ -42,7 +46,7 @@ module spi_master_io
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wire data_done;
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wire spi_wait;
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wire shift;
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wire spi_active;
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/*AUTOWIRE*/
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@ -76,24 +80,27 @@ module spi_master_io
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//# STATE MACHINE
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//#################################
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`define SPI_IDLE 2'b00 // set ss to 1
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`define SPI_SETUP 2'b01 // setup time
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`define SPI_DATA 2'b10 // send data
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`define SPI_HOLD 2'b11 // hold time
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`define SPI_IDLE 3'b000 // set ss to 1
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`define SPI_SETUP 3'b001 // setup time
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`define SPI_DATA 3'b010 // send data
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`define SPI_HOLD 3'b011 // hold time
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`define SPI_MARGIN 3'b100 // pause
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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spi_state[1:0] <= `SPI_IDLE;
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spi_state[2:0] <= `SPI_IDLE;
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else
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case (spi_state[1:0])
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case (spi_state[2:0])
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`SPI_IDLE :
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spi_state[1:0] <= fifo_read ? `SPI_SETUP : `SPI_IDLE;
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spi_state[2:0] <= fifo_read ? `SPI_SETUP : `SPI_IDLE;
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`SPI_SETUP :
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spi_state[1:0] <= phase_match ? `SPI_DATA : `SPI_SETUP;
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spi_state[2:0] <= phase_match ? `SPI_DATA : `SPI_SETUP;
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`SPI_DATA :
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spi_state[1:0] <= data_done ? `SPI_HOLD : `SPI_DATA;
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spi_state[2:0] <= data_done ? `SPI_HOLD : `SPI_DATA;
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`SPI_HOLD :
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spi_state[1:0] <= phase_match ? `SPI_IDLE : `SPI_HOLD;
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spi_state[2:0] <= phase_match ? `SPI_MARGIN : `SPI_HOLD;
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`SPI_MARGIN :
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spi_state[2:0] <= phase_match ? `SPI_IDLE : `SPI_MARGIN;
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endcase // case (spi_state[1:0])
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//read fifo on phase match (due to one cycle pipeline latency
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@ -102,9 +109,6 @@ module spi_master_io
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//data done whne
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assign data_done = fifo_empty & ~spi_wait & phase_match;
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//shift on every clock cycle while in datamode
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assign shift = phase_match & (spi_state[1:0]==`SPI_DATA);//period_match
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//load is the result of the fifo_read
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always @ (posedge clk)
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load_byte <= fifo_read;
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@ -113,18 +117,23 @@ module spi_master_io
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//# CHIP SELECT
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//#################################
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assign ss = (spi_state[1:0]==`SPI_IDLE);
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assign spi_active = ~(spi_state[2:0]==`SPI_IDLE | spi_state[2:0]==`SPI_MARGIN);
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assign ss = ~((spi_active & ~manual_mode) | (send_data & manual_mode));
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//#################################
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//# DRIVE OUTPUT CLOCK
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//#################################
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assign sclk = clkout & (spi_state[1:0]==`SPI_DATA);
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assign sclk = clkout & (spi_state[2:0]==`SPI_DATA);
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//#################################
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//# TX SHIFT REGISTER
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//#################################
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//shift on falling edge
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assign tx_shift = phase_match & (spi_state[2:0]==`SPI_DATA);
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oh_par2ser #(.PW(8),
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.SW(1))
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par2ser (// Outputs
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@ -135,7 +144,7 @@ module spi_master_io
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.clk (clk),
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.nreset (nreset), // async active low reset
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.din (fifo_dout[7:0]), // 8 bit data from fifo
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.shift (shift), // shift on neg edge
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.shift (tx_shift), // shift on neg edge
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.datasize (8'd7), // 8 bits at a time (0..7-->8)
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.load (load_byte), // load data from fifo
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.lsbfirst (lsbfirst), // serializer direction
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@ -146,12 +155,8 @@ module spi_master_io
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//# RX SHIFT REGISTER
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//#################################
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//generate access pulse at rise of ss
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oh_rise2pulse
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pulse (.out (rx_access),
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.nreset (nreset),
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.clk (clk),
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.in (ss));
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//shift in rising edge
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assign rx_shift = (spi_state[2:0] == `SPI_DATA) & period_match;
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oh_ser2par #(.PW(64),
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.SW(1))
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@ -161,7 +166,17 @@ module spi_master_io
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.din (miso), // serial data in
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.clk (clk), // shift clk
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.lsbfirst (lsbfirst), // shift direction
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.shift (shift)); // shift data
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.shift (rx_shift)); // shift data
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//generate access pulse at rise of ss
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always @ (posedge clk or negedge nreset)
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if(!nreset)
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ss_reg <= 1'b1;
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else
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ss_reg <= ss;
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assign rx_access = ss & ~ss_reg;
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endmodule // spi_master_io
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// Local Variables:
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@ -6,6 +6,7 @@
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//#############################################################################
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`include "spi_regmap.vh"
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module spi_master_regs # (parameter CLKDIV = 1, // default clkdiv
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parameter AW = 32, // addresss width
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parameter PW = 104 // packet width
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@ -14,7 +15,7 @@ module spi_master_regs # (parameter CLKDIV = 1, // default clkdiv
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//clk,reset, cfg
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input clk, // core clock
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input nreset, // async active low reset
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input hw_en, // block enable pin
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input hw_en, // block enable
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//io interface
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input [63:0] rx_data, // rx data
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input rx_access, // rx access pulse
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@ -23,8 +24,10 @@ module spi_master_regs # (parameter CLKDIV = 1, // default clkdiv
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output cpha, // clk phase shift (default is 0)
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output lsbfirst, // send lsbfirst
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output spi_en, // enable transmitter
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output manual_mode,// sets manual ss control
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output send_data, // controls ss in manual ss mode
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output reg [7:0] clkdiv_reg, // baud rate setting
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input [1:0] spi_state, // transmit state
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input [2:0] spi_state, // transmit state
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input fifo_prog_full, // fifo reached half/full
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input fifo_wait, // tx transfer wait
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//packet to transmit
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@ -113,6 +116,8 @@ module spi_master_regs # (parameter CLKDIV = 1, // default clkdiv
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assign cpol = config_reg[2]; // cpol
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assign cpha = config_reg[3]; // cpha
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assign lsbfirst = config_reg[4]; // send lsb first
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assign manual_mode = config_reg[5]; // manual control of ss bit
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assign send_data = config_reg[6]; // ss bit
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//####################################
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//# STATUS
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@ -124,10 +129,10 @@ module spi_master_regs # (parameter CLKDIV = 1, // default clkdiv
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else if(status_write)
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status_reg[7:0] <= reg_wdata[7:0];
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else
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status_reg[7:0] <= {5'b0, //7:3
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fifo_prog_full, //2
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|spi_state[1:0], //1
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(rx_access | status_reg[0])};//0
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status_reg[7:0] <= {5'b0, //7:4
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fifo_prog_full, //3
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1'b0, //reserved
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(rx_access | (~tx_write & status_reg[0]))};//0
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//####################################
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//# CLKDIV
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@ -1,5 +1,6 @@
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//#############################################################################
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//# Purpose: SPI slave IO state-machine #
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//# NOTE: only cpol=0, cpha=0 supported for now!! #
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//#############################################################################
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//# Author: Andreas Olofsson #
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//# License: MIT (see LICENSE file in OH! repository) #
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@ -44,13 +45,22 @@ module spi_slave_io #( parameter PW = 104 // packet width
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wire [63:0] tx_data;
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wire rx_shift;
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wire tx_load;
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wire tx_shift;
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wire tx_wait;
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wire ss_sync;
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wire ss_pulse;
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wire spi_fetch;
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wire byte_done;
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//#################################
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//# MODES: TODO!
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//#################################
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//cpol=0,cpha=0
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//(launch on negedge, capture on posedge)
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assign shift = ~ss & spi_en;
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assign rx_clk = sclk;
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assign tx_clk = ~sclk;
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assign tx_load = next_byte;
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//#################################
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//# STATE MACHINE
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@ -67,7 +77,7 @@ module spi_slave_io #( parameter PW = 104 // packet width
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else
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case (spi_state[1:0])
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`SPI_IDLE_STATE : spi_state[1:0] <= `SPI_CMD_STATE;
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`SPI_CMD_STATE : spi_state[1:0] <= byte_done ? `SPI_DATA_STATE : `SPI_CMD_STATE;
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`SPI_CMD_STATE : spi_state[1:0] <= next_byte ? `SPI_DATA_STATE : `SPI_CMD_STATE;
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`SPI_DATA_STATE : spi_state[1:0] <= `SPI_DATA_STATE;
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endcase // case (spi_state[1:0])
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@ -78,16 +88,19 @@ module spi_slave_io #( parameter PW = 104 // packet width
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else
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bit_count[7:0] <= bit_count[7:0] + 1'b1;
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assign next_byte = (spi_state[1:0]!=`SPI_IDLE_STATE) &
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(bit_count[2:0]==3'b000);
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assign byte_done = (spi_state[1:0]!=`SPI_IDLE_STATE) &
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(bit_count[2:0]==3'b000);
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(bit_count[2:0]==3'b111);
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// command/address register
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// auto increment for every byte
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always @ (negedge sclk or negedge nreset)
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always @ (posedge sclk or negedge nreset)
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if(!nreset)
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command_reg[7:0] <= 'b0;
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else if((spi_state[1:0]==`SPI_CMD_STATE) & byte_done)
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command_reg[7:0] <= rx_data[7:0];
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command_reg[7:0] <= spi_wdata[7:0];
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else if(byte_done)
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command_reg[7:0] <= {command_reg[7:6],
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command_reg[5:0] + 1'b1};
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@ -96,17 +109,17 @@ module spi_slave_io #( parameter PW = 104 // packet width
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//# SPI RX SHIFT REGISTER
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//#################################
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assign rx_shift = ~ss & spi_en;
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assign shift = ~ss & spi_en;
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oh_ser2par #(.PW(8),
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.SW(1))
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rx_ser2par (// Outputs
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.dout (rx_data[7:0]),
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// Inputs
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.clk (sclk),
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.clk (rx_clk),
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.din (mosi),
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.lsbfirst (lsbfirst), //msb first
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.shift (rx_shift));
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.shift (shift));
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//####################################
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//# REMOTE TRANSAXTION SHIFT REGISTER
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@ -117,27 +130,24 @@ module spi_slave_io #( parameter PW = 104 // packet width
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e_ser2par (// Outputs
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.dout (packet_out[PW-1:0]),
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// Inputs
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.clk (sclk),
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.clk (rx_clk),
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.din (mosi),
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.lsbfirst (lsbfirst), //msb first
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.shift (rx_shift));//rx_shift
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.shift (shift));//rx_shift
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//#################################
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//# TX SHIFT REGISTER
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//#################################
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assign tx_load = byte_done; // & (spi_state[1:0]==`SPI_CMD_STATE);
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assign tx_shift = ~ss & spi_en;
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oh_par2ser #(.PW(8),
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.SW(1))
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tx_par2ser (.dout (miso),
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.access_out (),
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.wait_out (tx_wait),
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.clk (sclk), // shift out on positive edge
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.clk (tx_clk), // shift out on positive edge
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.nreset (~ss),
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.din (spi_rdata[7:0]),
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.shift (tx_shift),
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.shift (shift),
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.lsbfirst (lsbfirst),
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.load (tx_load),
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.datasize (8'd7),
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@ -148,7 +158,7 @@ module spi_slave_io #( parameter PW = 104 // packet width
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//# REGISTER FILE INTERFACE
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//#################################
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assign spi_clk = sclk;
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assign spi_clk = rx_clk;
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assign spi_addr[5:0] = command_reg[5:0];
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@ -158,24 +168,24 @@ module spi_slave_io #( parameter PW = 104 // packet width
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(command_reg[7:6]==`SPI_WR) &
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(spi_state[1:0]==`SPI_DATA_STATE);
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assign spi_wdata[7:0] = rx_data[7:0];
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assign spi_wdata[7:0] = lsbfirst ? {mosi, rx_data[7:1]}
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: {rx_data[6:0], mosi};
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//###################################
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//# REMOTE FETCH LOGIC
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//###################################
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//sync the ss to free running clk
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//look for rising edge
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oh_dsync dsync (.dout (ss_sync),
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.clk (clk),
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.nreset(nreset),
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.din (ss));
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//create single cycle pulse
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oh_rise2pulse r2p (.out (ss_pulse),
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.clk (clk),
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.in (ss_sync));
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oh_rise2pulse r2p (.nreset (nreset),
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.out (ss_pulse),
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.clk (clk),
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.in (ss_sync));
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assign spi_fetch = ss_pulse & (command_reg[7:6]==`SPI_FETCH);
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@ -108,6 +108,14 @@ module spi_slave_regs #( parameter UREGS = 13, // # of user regs (max 48)
|
||||
assign lsbfirst = spi_config[4]; // lsb shifted in first
|
||||
assign valid = spi_config[5]; // user regs enable
|
||||
|
||||
//#####################################
|
||||
//# USER SPACE REGISTERS
|
||||
//#####################################
|
||||
|
||||
always @ (negedge spi_clk)
|
||||
if(user_write)
|
||||
user_regs[spi_addr[4:0]] <= spi_wdata[7:0];
|
||||
|
||||
//#####################################
|
||||
//# STATUS [1]
|
||||
//#####################################
|
||||
@ -127,13 +135,6 @@ module spi_slave_regs #( parameter UREGS = 13, // # of user regs (max 48)
|
||||
if(access_in)
|
||||
core_regs[63:0] <= core_data[63:0];
|
||||
|
||||
//#####################################
|
||||
//# USER SPACE REGISTERS
|
||||
//#####################################
|
||||
|
||||
always @ (negedge spi_clk)
|
||||
if(user_write)
|
||||
user_regs[spi_addr[4:0]] <= spi_wdata[7:0];
|
||||
|
||||
//#####################################
|
||||
//# REGISTER VECTOR (FOR FLEXIBILITY)
|
||||
|
||||
Loading…
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Reference in New Issue
Block a user