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Updating docs
-clarifications -removing TX DMA
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@ -2,8 +2,17 @@
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ELINK INTRODUCTION
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=====================================
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The "elink" is a low-latency/high-speed interface for communicating between FPGAs and ASICs (such as Epiphany). The interface can achieve a peak throughput of 8 Gbit/s (duplex) in modern FPGAs using 24 LVDS signal pairs.
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The "elink" is a low-latency/high-speed interface for communicating between FPGAs and ASICs (such as EpiphanyIII). The interface can achieve a peak throughput of 8 Gbit/s (duplex) in modern FPGAs using 24 LVDS signal pairs.
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###HOW TO SIMULATE
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```sh
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$ sudo apt-get install gtkwave iverilog
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$ git clone https://github.com/parallella/oh.git
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$ cd oh/elink/dv
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$ ./run.sh
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$ gtkwave test.vcd
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```
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###STRUCTURE
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![alt tag](docs/elink.png)
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@ -57,7 +66,7 @@ The default elink communication protocol uses source synchronous clocks, a packe
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_______________________________________________________________
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FRAME _/ \______
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DATA XXXX|B00|B01|B02|B03|B04|B05|B06|B07|B08|B09|B10|B11|B12|B13|B14.
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DATA XXXX|B00|B01|B02|B03|B04|B05|B06|B07|B08|B09|B10|B11|B12|B13|B14
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```
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@ -142,11 +151,11 @@ s_* |IO | AXI slave interface
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The following table shows the rough resource usage of the elink synthesized with the xc7z010clg400-1 as a target.
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(as of May 12, 2015)
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Instance |Module |Cells
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---------------------|-------------------------|------
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Instance |Module | FPGA Cells
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---------------------|-------------------------|------------
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elink |elink | 9809
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--ecfg_cdc |fifo_cdc | 994
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--eclocks |eclocks | 3
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--ecfg_cdc |fifo_cdc | 994
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--erx |erx | 5200
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----erx_core |erx_core | 2450
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------erx_cfg |erx_cfg | 174
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@ -183,8 +192,8 @@ REGISTER | AC | ADDRESS | DESCRIPTION
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---------------|----|---------|------------------
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E_RESET | -W | 0xF0200 | Soft reset
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E_CLK | -W | 0xF0204 | Clock configuration
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E_CHIPID | RW | 0xF0208 | Chip ID to drive to Epiphany pins
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***************|****|*********|********************
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E_CHIPID | RW | 0xF0208 | Chip ID for Epiphany pins
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***************|****|*********|**************************
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E_VERSION | RW | 0xF020C | Version number (static)
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ETX_CFG | RW | 0xF0210 | TX configuration
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ETX_STATUS | R- | 0xF0214 | TX status
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@ -226,7 +235,7 @@ Reset control register for the elink and Epiphany chip
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FIELD | DESCRIPTION
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-------- | --------------------------------------------------
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[0] | 0: active
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| 1: resets the elink and Epiphany chip
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| 1: resets elink and Epiphany chip
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###E_CLK (0xF0204) (NOT IMPLEMENTED)
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Transmit and Epiphany clock settings.
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@ -432,7 +441,6 @@ FIELD | DESCRIPTION
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[31:0] | Current transaction destination address to write to
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###DMAAUTO0 (0xF0514/0xF0534)
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Auto DMA register
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