diff --git a/elink/README.md b/elink/README.md index 24ff389..c44cb25 100644 --- a/elink/README.md +++ b/elink/README.md @@ -2,8 +2,17 @@ ELINK INTRODUCTION ===================================== -The "elink" is a low-latency/high-speed interface for communicating between FPGAs and ASICs (such as Epiphany). The interface can achieve a peak throughput of 8 Gbit/s (duplex) in modern FPGAs using 24 LVDS signal pairs. +The "elink" is a low-latency/high-speed interface for communicating between FPGAs and ASICs (such as EpiphanyIII). The interface can achieve a peak throughput of 8 Gbit/s (duplex) in modern FPGAs using 24 LVDS signal pairs. +###HOW TO SIMULATE +```sh +$ sudo apt-get install gtkwave iverilog +$ git clone https://github.com/parallella/oh.git +$ cd oh/elink/dv +$ ./run.sh +$ gtkwave test.vcd + +``` ###STRUCTURE ![alt tag](docs/elink.png) @@ -57,7 +66,7 @@ The default elink communication protocol uses source synchronous clocks, a packe _______________________________________________________________ FRAME _/ \______ - DATA XXXX|B00|B01|B02|B03|B04|B05|B06|B07|B08|B09|B10|B11|B12|B13|B14. + DATA XXXX|B00|B01|B02|B03|B04|B05|B06|B07|B08|B09|B10|B11|B12|B13|B14 ``` @@ -142,11 +151,11 @@ s_* |IO | AXI slave interface The following table shows the rough resource usage of the elink synthesized with the xc7z010clg400-1 as a target. (as of May 12, 2015) -Instance |Module |Cells ----------------------|-------------------------|------ +Instance |Module | FPGA Cells +---------------------|-------------------------|------------ elink |elink | 9809 - --ecfg_cdc |fifo_cdc | 994 --eclocks |eclocks | 3 + --ecfg_cdc |fifo_cdc | 994 --erx |erx | 5200 ----erx_core |erx_core | 2450 ------erx_cfg |erx_cfg | 174 @@ -183,8 +192,8 @@ REGISTER | AC | ADDRESS | DESCRIPTION ---------------|----|---------|------------------ E_RESET | -W | 0xF0200 | Soft reset E_CLK | -W | 0xF0204 | Clock configuration -E_CHIPID | RW | 0xF0208 | Chip ID to drive to Epiphany pins -***************|****|*********|******************** +E_CHIPID | RW | 0xF0208 | Chip ID for Epiphany pins +***************|****|*********|************************** E_VERSION | RW | 0xF020C | Version number (static) ETX_CFG | RW | 0xF0210 | TX configuration ETX_STATUS | R- | 0xF0214 | TX status @@ -226,7 +235,7 @@ Reset control register for the elink and Epiphany chip FIELD | DESCRIPTION -------- | -------------------------------------------------- [0] | 0: active - | 1: resets the elink and Epiphany chip + | 1: resets elink and Epiphany chip ###E_CLK (0xF0204) (NOT IMPLEMENTED) Transmit and Epiphany clock settings. @@ -432,7 +441,6 @@ FIELD | DESCRIPTION [31:0] | Current transaction destination address to write to - ###DMAAUTO0 (0xF0514/0xF0534) Auto DMA register diff --git a/elink/docs/elink.png b/elink/docs/elink.png index e36014a..c761715 100644 Binary files a/elink/docs/elink.png and b/elink/docs/elink.png differ diff --git a/elink/docs/elink.svg b/elink/docs/elink.svg index 08faba3..b8b530f 100644 --- a/elink/docs/elink.svg +++ b/elink/docs/elink.svg @@ -1371,7 +1371,7 @@ inkscape:pageshadow="2" inkscape:zoom="1" inkscape:cx="406.8708" - inkscape:cy="142.54407" + inkscape:cy="862.54407" inkscape:document-units="mm" inkscape:current-layer="layer1" showgrid="false" @@ -1502,7 +1502,7 @@ height="523.25903" x="-164.04877" y="305.38058" /> ETX_CFGIF - - ETX_DMA ETX_CFG - MiMIMiMI - Mi - Mi - - PI + PI + PI + MI