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Shorter, better names for rams

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aolofsson 2022-06-17 23:16:07 -04:00
parent 19074173ff
commit f938b7acac
4 changed files with 52 additions and 59 deletions
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4
src/stdlib/hdl/oh_memory_dp.v → src/stdlib/hdl/oh_dpram.v
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@ -1,11 +1,11 @@
//#############################################################################
//# Function: Dual Ported Memory #
//# Function: RAM (Dual Port)
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_memory_dp
module oh_dpram
#(parameter N = 32, // FIFO width
parameter DEPTH = 32, // FIFO depth
parameter REG = 1, // Register fifo output

51
src/stdlib/hdl/oh_fifo_async.v
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@ -151,36 +151,33 @@ module oh_fifo_async
//# Memory Array
//###########################
oh_memory_dp #(.N(N),
oh_dpram #(.N(N),
.DEPTH(DEPTH),
.REG(REG),
.TARGET(TARGET),
.SHAPE(SHAPE))
oh_memory_dp(.wr_wem ({(N){1'b1}}),
.wr_en (fifo_write),
/*AUTOINST*/
// Outputs
.rd_dout (rd_dout[N-1:0]),
// Inputs
.wr_clk (wr_clk),
.wr_addr (wr_addr[AW-1:0]),
.wr_din (wr_din[N-1:0]),
.rd_clk (rd_clk),
.rd_en (rd_en),
.rd_addr (rd_addr[AW-1:0]),
.bist_en (bist_en),
.bist_we (bist_we),
.bist_wem (bist_wem[N-1:0]),
.bist_addr (bist_addr[AW-1:0]),
.bist_din (bist_din[N-1:0]),
.shutdown (shutdown),
.vss (vss),
.vdd (vdd),
.vddio (vddio),
.memconfig (memconfig[7:0]),
.memrepair (memrepair[7:0]));
oh_dpram(.wr_wem ({(N){1'b1}}),
.wr_en (fifo_write),
/*AUTOINST*/
// Outputs
.rd_dout (rd_dout[N-1:0]),
// Inputs
.wr_clk (wr_clk),
.wr_addr (wr_addr[AW-1:0]),
.wr_din (wr_din[N-1:0]),
.rd_clk (rd_clk),
.rd_en (rd_en),
.rd_addr (rd_addr[AW-1:0]),
.bist_en (bist_en),
.bist_we (bist_we),
.bist_wem (bist_wem[N-1:0]),
.bist_addr (bist_addr[AW-1:0]),
.bist_din (bist_din[N-1:0]),
.shutdown (shutdown),
.vss (vss),
.vdd (vdd),
.vddio (vddio),
.memconfig (memconfig[7:0]),
.memrepair (memrepair[7:0]));
endmodule // oh_fifo_async
// Local Variables:
// verilog-library-directories:("." "../fpga/" "../dv")
// End:

52
src/stdlib/hdl/oh_fifo_sync.v
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@ -108,38 +108,34 @@ module oh_fifo_sync
//# Memory Array
//###########################
oh_memory_dp #(.N(N),
oh_dpram #(.N(N),
.DEPTH(DEPTH),
.REG(REG),
.SYN(SYN),
.TYPE(TYPE),
.SHAPE(SHAPE))
oh_memory_dp(.wr_wem ({(N){1'b1}}),
.wr_clk (clk),
.rd_clk (clk),
/*AUTOINST*/
// Outputs
.rd_dout (rd_dout[N-1:0]),
// Inputs
.wr_en (wr_en),
.wr_addr (wr_addr[AW-1:0]),
.wr_din (wr_din[N-1:0]),
.rd_en (rd_en),
.rd_addr (rd_addr[AW-1:0]),
.bist_en (bist_en),
.bist_we (bist_we),
.bist_wem (bist_wem[N-1:0]),
.bist_addr (bist_addr[AW-1:0]),
.bist_din (bist_din[N-1:0]),
.shutdown (shutdown),
.vss (vss),
.vdd (vdd),
.vddio (vddio),
.memconfig (memconfig[7:0]),
.memrepair (memrepair[7:0]));
oh_dpram(.wr_wem ({(N){1'b1}}),
.wr_clk (clk),
.rd_clk (clk),
/*AUTOINST*/
// Outputs
.rd_dout (rd_dout[N-1:0]),
// Inputs
.wr_en (wr_en),
.wr_addr (wr_addr[AW-1:0]),
.wr_din (wr_din[N-1:0]),
.rd_en (rd_en),
.rd_addr (rd_addr[AW-1:0]),
.bist_en (bist_en),
.bist_we (bist_we),
.bist_wem (bist_wem[N-1:0]),
.bist_addr (bist_addr[AW-1:0]),
.bist_din (bist_din[N-1:0]),
.shutdown (shutdown),
.vss (vss),
.vdd (vdd),
.vddio (vddio),
.memconfig (memconfig[7:0]),
.memrepair (memrepair[7:0]));
endmodule // oh_fifo_sync
// Local Variables:
// verilog-library-directories:("." "../dv" "../../fpu/hdl" "../../../oh/common/hdl")
// End:

4
src/stdlib/hdl/oh_memory_sp.v → src/stdlib/hdl/oh_ram.v
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@ -1,11 +1,11 @@
//#############################################################################
//# Function: Single Ported Memory #
//# Function: RAM (Single Port)
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_memory_sp
module oh_ram
#(parameter N = 32, // FIFO width
parameter DEPTH = 32, // FIFO depth
parameter REG = 1, // Register fifo output